mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
995b72ddda
This patch adds support for the X600 SPEAr600 based board. Its also the first SPEAr600 board that uses the newly introduced SPEAr600 SPL support. Xloader is not necessary any more. By using the new "u-boot.spr" make target, one image will generated containing both, U-Boot SPL (with mkimage header as needed by the SPEAr BootROM, and the main U-Boot with mkimage header. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Amit Virdi <amit.virdi@st.com> Cc: Vipin Kumar <vipin.kumar@st.com>
125 lines
3.2 KiB
C
125 lines
3.2 KiB
C
/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* Copyright (C) 2012 Stefan Roese <sr@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <nand.h>
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#include <netdev.h>
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#include <phy.h>
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#include <rtc.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/spr_defs.h>
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#include <asm/arch/spr_misc.h>
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#include <linux/mtd/fsmc_nand.h>
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#include "fpga.h"
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static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
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int board_init(void)
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{
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/*
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* X600 is equipped with an M41T82 RTC. This RTC has the
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* HT bit (Halt Update), which needs to be cleared upon
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* power-up. Otherwise the RTC is halted.
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*/
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rtc_reset();
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return spear_board_init(MACH_TYPE_SPEAR600);
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}
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int board_late_init(void)
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{
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/*
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* Monitor and env protection on by default
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*/
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flash_protect(FLAG_PROTECT_SET,
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CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE +
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CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN +
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2 * CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[0]);
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/* Init FPGA subsystem */
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x600_init_fpga();
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return 0;
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}
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/*
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* board_nand_init - Board specific NAND initialization
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* @nand: mtd private chip structure
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*
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* Called by nand_init_chip to initialize the board specific functions
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*/
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void board_nand_init(void)
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{
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struct misc_regs *const misc_regs_p =
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(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
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struct nand_chip *nand = &nand_chip[0];
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if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS))
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fsmc_nand_init(nand);
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}
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int designware_board_phy_init(struct eth_device *dev, int phy_addr,
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int (*mii_write)(struct eth_device *, u8, u8, u16),
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int dw_reset_phy(struct eth_device *))
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{
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/* Extended PHY control 1, select GMII */
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mii_write(dev, phy_addr, 23, 0x0020);
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/* Software reset necessary after GMII mode selction */
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dw_reset_phy(dev);
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/* Enable extended page register access */
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mii_write(dev, phy_addr, 31, 0x0001);
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/* 17e: Enhanced LED behavior, needs to be written twice */
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mii_write(dev, phy_addr, 17, 0x09ff);
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mii_write(dev, phy_addr, 17, 0x09ff);
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/* 16e: Enhanced LED method select */
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mii_write(dev, phy_addr, 16, 0xe0ea);
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/* Disable extended page register access */
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mii_write(dev, phy_addr, 31, 0x0000);
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/* Enable clock output pin */
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mii_write(dev, phy_addr, 18, 0x0049);
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int ret = 0;
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if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR,
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PHY_INTERFACE_MODE_GMII) >= 0)
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ret++;
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return ret;
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}
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