mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
01cdef22ee
Add a support for SPL which will boot from L2 LIM (0x0800_0000) and then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin) from MMC boot devices. SPL related code is leveraged from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
75 lines
1.3 KiB
C
75 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 SiFive, Inc
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*
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* Authors:
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* Pragnesh Patel <pragnesh.patel@sifive.com>
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*/
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#include <init.h>
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#include <spl.h>
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#include <misc.h>
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#include <log.h>
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#include <linux/delay.h>
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#include <asm/gpio.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/spl.h>
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#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
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int init_clk_and_ddr(void)
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{
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int ret;
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ret = soc_spl_init();
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if (ret) {
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debug("FU540 SPL init failed: %d\n", ret);
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return ret;
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}
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/*
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* GEMGXL init VSC8541 PHY reset sequence;
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* leave pull-down active for 2ms
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*/
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udelay(2000);
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ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset");
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if (ret) {
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debug("gem_phy_reset gpio request failed: %d\n", ret);
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return ret;
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}
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/* Set GPIO 12 (PHY NRESET) */
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ret = gpio_direction_output(GEM_PHY_RESET, 1);
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if (ret) {
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debug("gem_phy_reset gpio direction set failed: %d\n", ret);
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return ret;
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}
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udelay(1);
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/* Reset PHY again to enter unmanaged mode */
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gpio_set_value(GEM_PHY_RESET, 0);
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udelay(1);
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gpio_set_value(GEM_PHY_RESET, 1);
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mdelay(15);
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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ret = spl_early_init();
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if (ret)
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panic("spl_early_init() failed: %d\n", ret);
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arch_cpu_init_dm();
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preloader_console_init();
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ret = init_clk_and_ddr();
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if (ret)
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panic("init_clk_and_ddr() failed: %d\n", ret);
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}
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