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cdc9dd0750
Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying "okay" on respective board dts to use
the devicetree generated platdata.
Ex:
&spi1 {
status = "okay";
};
Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
30 lines
964 B
Plaintext
30 lines
964 B
Plaintext
Zynq SPI controller Device Tree Bindings
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----------------------------------------
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Required properties:
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- compatible : Should be "xlnx,spi-zynq".
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- reg : Physical base address and size of SPI registers map.
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- status : Status will be disabled in dtsi and enabled in required dts.
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- interrupt-parent : Must be core interrupt controller.
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- interrupts : Property with a value describing the interrupt
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number.
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- clocks : Clock phandles (see clock bindings for details).
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- clock-names : List of input clock names - "ref_clk", "pclk"
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(See clock bindings for details).
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- spi-max-frequency : Maximum SPI clocking speed of device in Hz
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Example:
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spi@e0006000 {
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compatible = "xlnx,zynq-spi";
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reg = <0xe0006000 0x1000>;
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status = "disabled";
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interrupt-parent = <&intc>;
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interrupts = <0 26 4>;
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clocks = <&clkc 25>, <&clkc 34>;
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clock-names = "ref_clk", "pclk";
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spi-max-frequency = <166666700>;
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#address-cells = <1>;
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#size-cells = <0>;
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} ;
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