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https://github.com/brain-hackers/u-boot-brain
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![Joe Hershberger](/assets/img/avatar_default.png)
Update the naming convention used in the network stack functions and variables that Ethernet drivers use to interact with it. This cleans up the temporary hacks that were added to this interface along with the DM support. This patch has a few remaining checkpatch.pl failures that would be out of the scope of this patch to fix (drivers that are in gross violation of checkpatch.pl). Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
573 lines
16 KiB
C
573 lines
16 KiB
C
/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <command.h>
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#include <config.h>
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#include <net.h>
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#include <miiphy.h>
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#undef ET_DEBUG
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#undef MII_DEBUG
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/* Ethernet Transmit and Receive Buffers */
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#define DBUF_LENGTH 1520
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#define PKT_MAXBUF_SIZE 1518
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#define PKT_MINBUF_SIZE 64
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#define PKT_MAXBLR_SIZE 1536
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#define LAST_PKTBUFSRX PKTBUFSRX - 1
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#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY)
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#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST)
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#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
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/* RxBD bits definitions */
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#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
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BD_ENET_RX_OV | BD_ENET_RX_TR)
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#include <asm/immap.h>
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#include <asm/fsl_mcdmafec.h>
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#include "MCD_dma.h"
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DECLARE_GLOBAL_DATA_PTR;
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struct fec_info_dma fec_info[] = {
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#ifdef CONFIG_SYS_FEC0_IOBASE
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{
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0, /* index */
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CONFIG_SYS_FEC0_IOBASE, /* io base */
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CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
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CONFIG_SYS_FEC0_MIIBASE, /* mii base */
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-1, /* phy_addr */
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0, /* duplex and speed */
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0, /* phy name */
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0, /* phyname init */
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0, /* RX BD */
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0, /* TX BD */
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0, /* rx Index */
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0, /* tx Index */
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0, /* tx buffer */
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0, /* initialized flag */
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(struct fec_info_dma *)-1, /* next */
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FEC0_RX_TASK, /* rxTask */
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FEC0_TX_TASK, /* txTask */
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FEC0_RX_PRIORITY, /* rxPri */
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FEC0_TX_PRIORITY, /* txPri */
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FEC0_RX_INIT, /* rxInit */
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FEC0_TX_INIT, /* txInit */
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0, /* usedTbdIndex */
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0, /* cleanTbdNum */
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},
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#endif
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#ifdef CONFIG_SYS_FEC1_IOBASE
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{
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1, /* index */
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CONFIG_SYS_FEC1_IOBASE, /* io base */
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CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
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CONFIG_SYS_FEC1_MIIBASE, /* mii base */
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-1, /* phy_addr */
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0, /* duplex and speed */
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0, /* phy name */
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0, /* phy name init */
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#ifdef CONFIG_SYS_DMA_USE_INTSRAM
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(cbd_t *)DBUF_LENGTH, /* RX BD */
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#else
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0, /* RX BD */
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#endif
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0, /* TX BD */
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0, /* rx Index */
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0, /* tx Index */
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0, /* tx buffer */
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0, /* initialized flag */
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(struct fec_info_dma *)-1, /* next */
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FEC1_RX_TASK, /* rxTask */
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FEC1_TX_TASK, /* txTask */
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FEC1_RX_PRIORITY, /* rxPri */
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FEC1_TX_PRIORITY, /* txPri */
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FEC1_RX_INIT, /* rxInit */
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FEC1_TX_INIT, /* txInit */
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0, /* usedTbdIndex */
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0, /* cleanTbdNum */
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}
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#endif
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};
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static int fec_send(struct eth_device *dev, void *packet, int length);
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static int fec_recv(struct eth_device *dev);
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static int fec_init(struct eth_device *dev, bd_t * bd);
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static void fec_halt(struct eth_device *dev);
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#ifdef ET_DEBUG
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static void dbg_fec_regs(struct eth_device *dev)
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{
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struct fec_info_dma *info = dev->priv;
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volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
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printf("=====\n");
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printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
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printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
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printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
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printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
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printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
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printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
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printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
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printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
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printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
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printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
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printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
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printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
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printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
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printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
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printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
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printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
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printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
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printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
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printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
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printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
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printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
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printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
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printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
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printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
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printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
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printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
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printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
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printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
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printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
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printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
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printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
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printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
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printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
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printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
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printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
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}
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#endif
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static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd,
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int dup_spd)
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{
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if ((dup_spd >> 16) == FULL) {
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/* Set maximum frame length */
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fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
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FEC_RCR_PROM | 0x100;
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fecp->tcr = FEC_TCR_FDEN;
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} else {
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/* Half duplex mode */
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fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
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FEC_RCR_MII_MODE | FEC_RCR_DRT;
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fecp->tcr &= ~FEC_TCR_FDEN;
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}
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if ((dup_spd & 0xFFFF) == _100BASET) {
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#ifdef MII_DEBUG
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printf("100Mbps\n");
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#endif
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bd->bi_ethspeed = 100;
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} else {
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#ifdef MII_DEBUG
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printf("10Mbps\n");
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#endif
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bd->bi_ethspeed = 10;
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}
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}
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static int fec_send(struct eth_device *dev, void *packet, int length)
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{
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struct fec_info_dma *info = dev->priv;
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cbd_t *pTbd, *pUsedTbd;
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u16 phyStatus;
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miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
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/* process all the consumed TBDs */
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while (info->cleanTbdNum < CONFIG_SYS_TX_ETH_BUFFER) {
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pUsedTbd = &info->txbd[info->usedTbdIdx];
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if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) {
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#ifdef ET_DEBUG
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printf("Cannot clean TBD %d, in use\n",
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info->cleanTbdNum);
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#endif
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return 0;
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}
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/* clean this buffer descriptor */
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if (info->usedTbdIdx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
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pUsedTbd->cbd_sc = BD_ENET_TX_WRAP;
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else
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pUsedTbd->cbd_sc = 0;
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/* update some indeces for a correct handling of the TBD ring */
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info->cleanTbdNum++;
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info->usedTbdIdx = (info->usedTbdIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
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}
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/* Check for valid length of data. */
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if ((length > 1500) || (length <= 0)) {
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return -1;
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}
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/* Check the number of vacant TxBDs. */
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if (info->cleanTbdNum < 1) {
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printf("No available TxBDs ...\n");
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return -1;
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}
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/* Get the first TxBD to send the mac header */
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pTbd = &info->txbd[info->txIdx];
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pTbd->cbd_datlen = length;
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pTbd->cbd_bufaddr = (u32) packet;
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pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
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info->txIdx = (info->txIdx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
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/* Enable DMA transmit task */
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MCD_continDma(info->txTask);
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info->cleanTbdNum -= 1;
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/* wait until frame is sent . */
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while (pTbd->cbd_sc & BD_ENET_TX_READY) {
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udelay(10);
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}
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return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
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}
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static int fec_recv(struct eth_device *dev)
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{
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struct fec_info_dma *info = dev->priv;
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volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
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cbd_t *prbd = &info->rxbd[info->rxIdx];
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u32 ievent;
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int frame_length, len = 0;
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/* Check if any critical events have happened */
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ievent = fecp->eir;
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if (ievent != 0) {
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fecp->eir = ievent;
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if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
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printf("fec_recv: error\n");
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fec_halt(dev);
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fec_init(dev, NULL);
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return 0;
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}
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if (ievent & FEC_EIR_HBERR) {
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/* Heartbeat error */
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fecp->tcr |= FEC_TCR_GTS;
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}
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if (ievent & FEC_EIR_GRA) {
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/* Graceful stop complete */
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if (fecp->tcr & FEC_TCR_GTS) {
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printf("fec_recv: tcr_gts\n");
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fec_halt(dev);
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fecp->tcr &= ~FEC_TCR_GTS;
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fec_init(dev, NULL);
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}
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}
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}
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if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
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if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
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!(prbd->cbd_sc & BD_ENET_RX_ERR) &&
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((prbd->cbd_datlen - 4) > 14)) {
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/* Get buffer address and size */
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frame_length = prbd->cbd_datlen - 4;
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/* Fill the buffer and pass it to upper layers */
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net_process_received_packet((uchar *)prbd->cbd_bufaddr,
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frame_length);
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len = frame_length;
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}
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/* Reset buffer descriptor as empty */
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if ((info->rxIdx) == (PKTBUFSRX - 1))
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prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
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else
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prbd->cbd_sc = BD_ENET_RX_EMPTY;
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prbd->cbd_datlen = PKTSIZE_ALIGN;
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/* Now, we have an empty RxBD, restart the DMA receive task */
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MCD_continDma(info->rxTask);
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/* Increment BD count */
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info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX;
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}
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return len;
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}
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static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac)
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{
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u8 currByte; /* byte for which to compute the CRC */
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int byte; /* loop - counter */
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int bit; /* loop - counter */
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u32 crc = 0xffffffff; /* initial value */
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for (byte = 0; byte < 6; byte++) {
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currByte = mac[byte];
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for (bit = 0; bit < 8; bit++) {
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if ((currByte & 0x01) ^ (crc & 0x01)) {
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crc >>= 1;
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crc = crc ^ 0xedb88320;
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} else {
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crc >>= 1;
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}
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currByte >>= 1;
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}
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}
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crc = crc >> 26;
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/* Set individual hash table register */
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if (crc >= 32) {
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fecp->ialr = (1 << (crc - 32));
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fecp->iaur = 0;
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} else {
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fecp->ialr = 0;
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fecp->iaur = (1 << crc);
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}
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/* Set physical address */
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fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
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fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
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/* Clear multicast address hash table */
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fecp->gaur = 0;
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fecp->galr = 0;
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}
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static int fec_init(struct eth_device *dev, bd_t * bd)
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{
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struct fec_info_dma *info = dev->priv;
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volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
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int i;
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uchar enetaddr[6];
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#ifdef ET_DEBUG
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printf("fec_init: iobase 0x%08x ...\n", info->iobase);
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#endif
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fecpin_setclear(dev, 1);
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fec_halt(dev);
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#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
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defined (CONFIG_SYS_DISCOVER_PHY)
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mii_init();
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set_fec_duplex_speed(fecp, bd, info->dup_spd);
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#else
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#ifndef CONFIG_SYS_DISCOVER_PHY
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set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
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#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
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#endif /* CONFIG_CMD_MII || CONFIG_MII */
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/* We use strictly polling mode only */
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fecp->eimr = 0;
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/* Clear any pending interrupt */
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fecp->eir = 0xffffffff;
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/* Set station address */
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if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE)
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eth_getenv_enetaddr("ethaddr", enetaddr);
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else
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eth_getenv_enetaddr("eth1addr", enetaddr);
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fec_set_hwaddr(fecp, enetaddr);
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/* Set Opcode/Pause Duration Register */
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fecp->opd = 0x00010020;
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/* Setup Buffers and Buffer Desriptors */
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info->rxIdx = 0;
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info->txIdx = 0;
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/* Setup Receiver Buffer Descriptors (13.14.24.18)
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* Settings: Empty, Wrap */
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for (i = 0; i < PKTBUFSRX; i++) {
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info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
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info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
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info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
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}
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info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
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/* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
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* Settings: Last, Tx CRC */
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for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
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info->txbd[i].cbd_sc = 0;
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info->txbd[i].cbd_datlen = 0;
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info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
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}
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info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
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info->usedTbdIdx = 0;
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info->cleanTbdNum = CONFIG_SYS_TX_ETH_BUFFER;
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/* Set Rx FIFO alarm and granularity value */
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fecp->rfcr = 0x0c000000;
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fecp->rfar = 0x0000030c;
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/* Set Tx FIFO granularity value */
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fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
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fecp->tfar = 0x00000080;
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fecp->tfwr = 0x2;
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fecp->ctcwr = 0x03000000;
|
|
|
|
/* Enable DMA receive task */
|
|
MCD_startDma(info->rxTask, /* Dma channel */
|
|
(s8 *) info->rxbd, /*Source Address */
|
|
0, /* Source increment */
|
|
(s8 *) (&fecp->rfdr), /* dest */
|
|
4, /* dest increment */
|
|
0, /* DMA size */
|
|
4, /* xfer size */
|
|
info->rxInit, /* initiator */
|
|
info->rxPri, /* priority */
|
|
(MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */
|
|
(MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */
|
|
);
|
|
|
|
/* Enable DMA tx task with no ready buffer descriptors */
|
|
MCD_startDma(info->txTask, /* Dma channel */
|
|
(s8 *) info->txbd, /*Source Address */
|
|
0, /* Source increment */
|
|
(s8 *) (&fecp->tfdr), /* dest */
|
|
4, /* dest incr */
|
|
0, /* DMA size */
|
|
4, /* xfer size */
|
|
info->txInit, /* initiator */
|
|
info->txPri, /* priority */
|
|
(MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */
|
|
(MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */
|
|
);
|
|
|
|
/* Now enable the transmit and receive processing */
|
|
fecp->ecr |= FEC_ECR_ETHER_EN;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void fec_halt(struct eth_device *dev)
|
|
{
|
|
struct fec_info_dma *info = dev->priv;
|
|
volatile fecdma_t *fecp = (fecdma_t *) (info->iobase);
|
|
int counter = 0xffff;
|
|
|
|
/* issue graceful stop command to the FEC transmitter if necessary */
|
|
fecp->tcr |= FEC_TCR_GTS;
|
|
|
|
/* wait for graceful stop to register */
|
|
while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ;
|
|
|
|
/* Disable DMA tasks */
|
|
MCD_killDma(info->txTask);
|
|
MCD_killDma(info->rxTask);;
|
|
|
|
/* Disable the Ethernet Controller */
|
|
fecp->ecr &= ~FEC_ECR_ETHER_EN;
|
|
|
|
/* Clear FIFO status registers */
|
|
fecp->rfsr &= FIFO_ERRSTAT;
|
|
fecp->tfsr &= FIFO_ERRSTAT;
|
|
|
|
fecp->frst = 0x01000000;
|
|
|
|
/* Issue a reset command to the FEC chip */
|
|
fecp->ecr |= FEC_ECR_RESET;
|
|
|
|
/* wait at least 20 clock cycles */
|
|
udelay(10000);
|
|
|
|
#ifdef ET_DEBUG
|
|
printf("Ethernet task stopped\n");
|
|
#endif
|
|
}
|
|
|
|
int mcdmafec_initialize(bd_t * bis)
|
|
{
|
|
struct eth_device *dev;
|
|
int i;
|
|
#ifdef CONFIG_SYS_DMA_USE_INTSRAM
|
|
u32 tmp = CONFIG_SYS_INTSRAM + 0x2000;
|
|
#endif
|
|
|
|
for (i = 0; i < ARRAY_SIZE(fec_info); i++) {
|
|
|
|
dev =
|
|
(struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
|
|
sizeof *dev);
|
|
if (dev == NULL)
|
|
hang();
|
|
|
|
memset(dev, 0, sizeof(*dev));
|
|
|
|
sprintf(dev->name, "FEC%d", fec_info[i].index);
|
|
|
|
dev->priv = &fec_info[i];
|
|
dev->init = fec_init;
|
|
dev->halt = fec_halt;
|
|
dev->send = fec_send;
|
|
dev->recv = fec_recv;
|
|
|
|
/* setup Receive and Transmit buffer descriptor */
|
|
#ifdef CONFIG_SYS_DMA_USE_INTSRAM
|
|
fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
|
|
tmp = (u32)fec_info[i].rxbd;
|
|
fec_info[i].txbd =
|
|
(cbd_t *)((u32)fec_info[i].txbd + tmp +
|
|
(PKTBUFSRX * sizeof(cbd_t)));
|
|
tmp = (u32)fec_info[i].txbd;
|
|
fec_info[i].txbuf =
|
|
(char *)((u32)fec_info[i].txbuf + tmp +
|
|
(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
|
|
tmp = (u32)fec_info[i].txbuf;
|
|
#else
|
|
fec_info[i].rxbd =
|
|
(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
|
|
(PKTBUFSRX * sizeof(cbd_t)));
|
|
fec_info[i].txbd =
|
|
(cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
|
|
(CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
|
|
fec_info[i].txbuf =
|
|
(char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
|
|
#endif
|
|
|
|
#ifdef ET_DEBUG
|
|
printf("rxbd %x txbd %x\n",
|
|
(int)fec_info[i].rxbd, (int)fec_info[i].txbd);
|
|
#endif
|
|
|
|
fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
|
|
|
|
eth_register(dev);
|
|
|
|
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
|
|
miiphy_register(dev->name,
|
|
mcffec_miiphy_read, mcffec_miiphy_write);
|
|
#endif
|
|
|
|
if (i > 0)
|
|
fec_info[i - 1].next = &fec_info[i];
|
|
}
|
|
fec_info[i - 1].next = &fec_info[0];
|
|
|
|
/* default speed */
|
|
bis->bi_ethspeed = 10;
|
|
|
|
return 0;
|
|
}
|