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https://github.com/brain-hackers/u-boot-brain
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e40ac4870c
The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC and boot from eSPI. When power on, the porcessor excutes the ROM code to initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from the memory device that interfaced to the controller, such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. The memory device should contain a specific data structure with control word and config word at the fixed address. The config word direct the process how to config the memory device, and the control word direct the processor where to find the image on the memory device, or where copy the main image to. The user can use any method to store the data structure to the memory device, only if store it on the assigned address. The on-chip ROM code will map the whole 4GB address space by setting entry0 in the TLB1, so the main image need to switch to Address space 1 to disable this mapping and map the address space again. This patch implements loading the mian U-Boot image into L2SRAM, so the image can configure the system memory by using SPD EEPROM. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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| .. | ||
| config.mk | ||
| ddr.c | ||
| law.c | ||
| Makefile | ||
| mpc8536ds.c | ||
| tlb.c | ||