mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 13:46:17 +09:00
c37207d7f5
U-Boot allows for configurable prompt strings using the CONFIG_AUTOBOOT_PROMPT resp. CONFIG_MENUPROMPT definitions. So far, the assumption was that any such user defined problts would contain exactly one "%d" format specifier. But some boards did not. To allow for flexible boot prompts without adding too complex code we now allow to specify the whole list of printf() arguments in the user definition. This is powerful, but requires a responsible user who really understands what he is doing, as he needs to know for exanple which variables are available in the respective context. Signed-off-by: Wolfgang Denk <wd@denx.de>
390 lines
13 KiB
C
390 lines
13 KiB
C
/*
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* Parameters for GTH board
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* Based on FADS860T
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* by thomas.lange@corelatus.com
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* A collection of structures, addresses, and values associated with
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* the Motorola 860T FADS board. Copied from the MBX stuff.
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* Magnus Damm added defines for 8xxrom and extended bd_info.
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* Helmut Buchsbaum added bitvalues for BCSRx
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*
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* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
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*/
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/*
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* ff000000 -> ff00ffff : IMAP internal in the cpu
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* e0000000 -> ennnnnnn : pcmcia
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* 98000000 -> 983nnnnn : FPGA 4MB
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* 90000000 -> 903nnnnn : FPGA 4MB
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* 80000000 -> 80nnnnnn : flash connected to CS0, final ( real ) location
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* 00000000 -> nnnnnnnn : sdram
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*/
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/* ------------------------------------------------------------------------- */
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#include <mpc8xx_irq.h>
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#define CONFIG_MPC860 1
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#define CONFIG_MPC860T 1
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#define CONFIG_GTH 1
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#define CONFIG_MISC_INIT_R 1
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#undef CONFIG_8xx_CONS_SMC2
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#undef CONFIG_8xx_CONS_NONE
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define MPC8XX_FACT 3 /* Multiply by 3 */
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#define MPC8XX_XIN 16384000 /* 16.384 MHz */
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#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
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#define CONFIG_BOOTDELAY 1 /* autoboot after 0 seconds */
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#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */
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#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */
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#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */
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/* Only interrupt boot if space is pressed */
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/* If a long serial cable is connected but */
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/* other end is dead, garbage will be read */
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#define CONFIG_AUTOBOOT_KEYED 1
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#define CONFIG_AUTOBOOT_PROMPT \
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"Press space to abort autoboot in %d second\n", bootdelay
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#define CONFIG_AUTOBOOT_DELAY_STR "d"
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#define CONFIG_AUTOBOOT_STOP_STR " "
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#if 0
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/* Net boot */
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/* Loads a tftp image and starts it */
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#define CONFIG_BOOTCOMMAND "bootp;bootm 100000" /* autoboot command */
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#define CONFIG_BOOTARGS "panic=1"
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#else
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/* Compact flash boot */
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#define CONFIG_BOOTARGS "panic=1 root=/dev/hda7"
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#define CONFIG_BOOTCOMMAND "disk 100000 0:5;bootm 100000"
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#endif
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/* Enable watchdog */
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#define CONFIG_WATCHDOG 1
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/* choose SCC1 ethernet (10BASET on motherboard)
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* or FEC ethernet (10/100 on daughterboard)
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*/
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#if 1
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#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
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#undef CONFIG_FEC_ENET /* disable FEC ethernet */
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#define CFG_DISCOVER_PHY
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#else
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#undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */
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#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
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#define CFG_DISCOVER_PHY
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#endif
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#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
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#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_IDE
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#define CONFIG_MAC_PARTITION
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#define CONFIG_DOS_PARTITION
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_PROMPT "=>" /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
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/* Default location to load data from net */
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#define CFG_LOAD_ADDR 0x100000
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400 }
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CFG_IMMR 0xFF000000
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#define CFG_IMMR_SIZE ((uint)(64 * 1024))
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CFG_INIT_RAM_ADDR CFG_IMMR
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#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x80000000
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#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
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#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_ENV_IS_IN_FLASH 1
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#undef CFG_ENV_IS_IN_EEPROM
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#define CFG_ENV_OFFSET 0x000E0000
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#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
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#define CFG_ENV_SECT_SIZE 0x50000 /* see README - env sector total size */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#if defined(CONFIG_WATCHDOG)
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
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SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
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#else
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#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
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#endif
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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* PCMCIA config., multi-function pin tri-state
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*/
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#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*----------------------------------------------------------------------
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* RTCSC - Real-Time Clock Status and Control Register 11-27
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*-----------------------------------------------------------------------
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*/
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/*FIXME dont use for now */
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/*#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
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/*#define CFG_RTCSC (RTCSC_RTF) */
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CFG_PISCR (PISCR_PS | PISCR_PITF)
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/* PITE */
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/*-----------------------------------------------------------------------
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* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
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*-----------------------------------------------------------------------
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* set the PLL, the low-power modes and the reset control (15-29)
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*/
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#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
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PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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/* FIXME check values */
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#define SCCR_MASK SCCR_EBDF11
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#define CFG_SCCR (SCCR_TBS|SCCR_RTSEL|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
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/*-----------------------------------------------------------------------
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*
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*-----------------------------------------------------------------------
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*
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*/
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#define CFG_DER 0
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/* Because of the way the 860 starts up and assigns CS0 the
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* entire address space, we have to set the memory controller
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* differently. Normally, you write the option register
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* first, and then enable the chip select by writing the
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* base register. For CS0, you must write the base register
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* first, followed by the option register.
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*/
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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/* the other CS:s are determined by looking at parameters in BCSRx */
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#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
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#define CFG_REMAP_OR_AM 0xFF800000 /* 4 MB OR addr mask */
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#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
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#define FPGA_2_BASE 0x90000000
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#define FPGA_3_BASE 0x98000000
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/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
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#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
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#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
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#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
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#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16 )
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CONFIG_ETHADDR DE:AD:BE:EF:00:01 /* Ethernet address */
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#ifdef CONFIG_MPC860T
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/* Interrupt level assignments.
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*/
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#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
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#endif /* CONFIG_MPC860T */
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/* We don't use the 8259.
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*/
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#define NR_8259_INTS 0
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/* Machine type
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*/
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#define _MACH_8xx (_MACH_gth)
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#ifdef CONFIG_MPC860
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#define PCMCIA_SLOT_A 1
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#define CONFIG_PCMCIA_SLOT_A 1
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#endif
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#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
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#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
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#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
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#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
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#define CFG_PCMCIA_IO_ADDR (0xEC000000)
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#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
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#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
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#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
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#undef CONFIG_IDE_LED /* LED for ide not supported */
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#undef CONFIG_IDE_RESET /* reset for ide not supported */
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
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#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
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/* Offset for data I/O */
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#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for normal register accesses */
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#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
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/* Offset for alternate registers */
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#define CFG_ATA_ALT_OFFSET 0x0100
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#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
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#define PA_FRONT_LED ((u16)0x4) /* PA 13 */
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#define PA_FL_CONFIG ((u16)0x20) /* PA 10 */
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#define PA_FL_CE ((u16)0x1000) /* PA 3 */
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#define PB_ID_GND ((u32)1) /* PB 31 */
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#define PB_REV_1 ((u32)2) /* PB 30 */
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#define PB_REV_0 ((u32)4) /* PB 29 */
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#define PB_BLUE_LED ((u32)0x400) /* PB 21 */
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#define PB_EEPROM ((u32)0x800) /* PB 20 */
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#define PB_ID_3 ((u32)0x2000) /* PB 18 */
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#define PB_ID_2 ((u32)0x4000) /* PB 17 */
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#define PB_ID_1 ((u32)0x8000) /* PB 16 */
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#define PB_ID_0 ((u32)0x10000) /* PB 15 */
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/* NOTE. This is reset for 100Mbit port only */
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#define PC_ENET100_RESET ((ushort)0x0080) /* PC 8 */
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#endif /* __CONFIG_H */
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