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https://github.com/brain-hackers/u-boot-brain
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eee20f8132
Add SDHCI host controller found on STMicroelectronics SoCs On some ST SoCs, i.e. STiH407/STiH410, the MMC devices can live inside a dedicated flashSS sub-system that provides an extend subset of registers that can be used to configure the Arasan MMC/SD Host Controller. This means, that the SDHCI Arasan Controller can be configured to be eMMC4.5 or 4.3 spec compliant. W/o these settings the SDHCI will configure and use the MMC/SD controller with limited features e.g. PIO mode, no DMA, no HS etc. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
69 lines
2.1 KiB
C
69 lines
2.1 KiB
C
/*
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* (C) Copyright 2017 Patrice Chotard <patrice.chotard@st.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __STI_SDHCI_H__
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#define __STI_SDHCI_H__
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#define FLASHSS_MMC_CORE_CONFIG_1 0x400
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#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ BIT(24)
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#define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN BIT(12)
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#define STI_FLASHSS_MMC_CORE_CONFIG_1 \
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(FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ | \
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FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN)
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#define FLASHSS_MMC_CORE_CONFIG_2 0x404
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#define FLASHSS_MMC_CORECFG_HIGH_SPEED BIT(28)
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#define FLASHSS_MMC_CORECFG_8BIT_EMMC BIT(20)
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#define MAX_BLK_LENGTH_1024 BIT(16)
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#define BASE_CLK_FREQ_200 0xc8
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#define STI_FLASHSS_MMC_CORE_CONFIG2 \
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(FLASHSS_MMC_CORECFG_HIGH_SPEED | \
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FLASHSS_MMC_CORECFG_8BIT_EMMC | \
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MAX_BLK_LENGTH_1024 | \
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BASE_CLK_FREQ_200 << 0)
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#define STI_FLASHSS_SDCARD_CORE_CONFIG2 \
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(FLASHSS_MMC_CORECFG_HIGH_SPEED | \
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MAX_BLK_LENGTH_1024 | \
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BASE_CLK_FREQ_200)
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#define FLASHSS_MMC_CORE_CONFIG_3 0x408
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#define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC BIT(28)
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#define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT BIT(20)
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#define FLASHSS_MMC_CORECFG_3P3_VOLT BIT(8)
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#define FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT BIT(4)
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#define FLASHSS_MMC_CORECFG_SDMA BIT(0)
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#define STI_FLASHSS_MMC_CORE_CONFIG3 \
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(FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC | \
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FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \
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FLASHSS_MMC_CORECFG_3P3_VOLT | \
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FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \
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FLASHSS_MMC_CORECFG_SDMA)
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#define STI_FLASHSS_SDCARD_CORE_CONFIG3 \
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(FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT | \
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FLASHSS_MMC_CORECFG_3P3_VOLT | \
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FLASHSS_MMC_CORECFG_SUSP_RES_SUPPORT | \
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FLASHSS_MMC_CORECFG_SDMA)
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#define FLASHSS_MMC_CORE_CONFIG_4 0x40c
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#define FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT BIT(20)
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#define FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT BIT(16)
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#define FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT BIT(12)
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#define STI_FLASHSS_MMC_CORE_CONFIG4 \
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(FLASHSS_MMC_CORECFG_D_DRIVER_SUPPORT | \
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FLASHSS_MMC_CORECFG_C_DRIVER_SUPPORT | \
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FLASHSS_MMC_CORECFG_A_DRIVER_SUPPORT)
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#define ST_MMC_CCONFIG_REG_5 0x210
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#define SYSCONF_MMC1_ENABLE_BIT 3
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#endif /* _STI_SDHCI_H_ */
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