mirror of
https://github.com/brain-hackers/u-boot-brain
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21b29fc64e
Compared to the Armada 3700, the Armada 7K and 8K are much more on the high-end side: they use a dual Cortex-A72 or a quad Cortex-A72, as opposed to the Cortex-A53 for the Armada 3700. The Armada 7K and 8K also use a fairly unique architecture, internally they are composed of several components: - One AP (Application Processor), which contains the processor itself and a few core hardware blocks. The AP used in the Armada 7K and 8K is called AP806, and is available in two configurations: dual Cortex-A72 and quad Cortex-A72. - One or two CP (Communication Processor), which contain most of the I/O interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP, while the 8K family chips integrate two CPs, providing two times the number of I/O interfaces available in the CP. The CP used in the 7K and 8K is called CP110. All in all, this gives the following combinations: - Armada 7020, which is a dual Cortex-A72 with one CP - Armada 7040, which is a quad Cortex-A72 with one CP - Armada 8020, which is a dual Cortex-A72 with two CPs - Armada 8040, which is a quad Cortex-A72 with two CPs This patch adds basic support for this ARMv8 based SoC into U-Boot. Future patches will integrate other device drivers and board support, starting with the Marvell DB-88F7040 development board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com>
82 lines
1.6 KiB
C
82 lines
1.6 KiB
C
/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <libfdt.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <asm/armv8/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Armada 3700 */
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#define MVEBU_GPIO_NB_REG_BASE (MVEBU_REGISTER(0x13800))
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#define MVEBU_TEST_PIN_LATCH_N (MVEBU_GPIO_NB_REG_BASE + 0x8)
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#define MVEBU_XTAL_MODE_MASK BIT(9)
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#define MVEBU_XTAL_MODE_OFFS 9
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#define MVEBU_XTAL_CLOCK_25MHZ 0x0
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#define MVEBU_XTAL_CLOCK_40MHZ 0x1
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#define MVEBU_NB_WARM_RST_REG (MVEBU_GPIO_NB_REG_BASE + 0x40)
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#define MVEBU_NB_WARM_RST_MAGIC_NUM 0x1d1e
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static struct mm_region mvebu_mem_map[] = {
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{
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/* RAM */
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.phys = 0x0UL,
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.virt = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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},
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{
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/* SRAM, MMIO regions */
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.phys = 0xd0000000UL,
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.virt = 0xd0000000UL,
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.size = 0x02000000UL, /* 32MiB internal registers */
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE
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},
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{
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = mvebu_mem_map;
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void reset_cpu(ulong ignored)
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{
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/*
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* Write magic number of 0x1d1e to North Bridge Warm Reset register
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* to trigger warm reset
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*/
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writel(MVEBU_NB_WARM_RST_MAGIC_NUM, MVEBU_NB_WARM_RST_REG);
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}
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/*
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* get_ref_clk
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*
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* return: reference clock in MHz (25 or 40)
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*/
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u32 get_ref_clk(void)
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{
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u32 regval;
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regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
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MVEBU_XTAL_MODE_OFFS;
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if (regval == MVEBU_XTAL_CLOCK_25MHZ)
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return 25;
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else
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return 40;
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}
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