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https://github.com/brain-hackers/u-boot-brain
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78c627cf1f
The clock enable bits for UMC are more SoC-specific than for the other hardware blocks. Separate the UMC clocks and the other clocks for better code reuse across SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
36 lines
786 B
C
36 lines
786 B
C
/*
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* Copyright (C) 2015-2017 Socionext Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/io.h>
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#include "../init.h"
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#include "../sc-regs.h"
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void uniphier_pro5_dram_clk_init(void)
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{
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u32 tmp;
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/*
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* deassert reset
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* UMCA2: Ch1 (DDR3)
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* UMCA1, UMC31: Ch0 (WIO1)
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* UMCA0, UMC30: Ch0 (WIO0)
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*/
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tmp = readl(SC_RSTCTRL4);
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tmp |= SC_RSTCTRL4_NRST_UMCSB | SC_RSTCTRL4_NRST_UMCA2 |
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SC_RSTCTRL4_NRST_UMCA1 | SC_RSTCTRL4_NRST_UMCA0 |
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SC_RSTCTRL4_NRST_UMC31 | SC_RSTCTRL4_NRST_UMC30;
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writel(tmp, SC_RSTCTRL4);
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readl(SC_RSTCTRL4); /* dummy read */
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/* provide clocks */
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tmp = readl(SC_CLKCTRL4);
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tmp |= SC_CLKCTRL4_CEN_UMCSB | SC_CLKCTRL4_CEN_UMC1 |
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SC_CLKCTRL4_CEN_UMC0;
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writel(tmp, SC_CLKCTRL4);
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readl(SC_CLKCTRL4); /* dummy read */
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}
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