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4075928c36
This patch adds reset controller bits definition header file for MediaTek MT7620 SoC Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
36 lines
738 B
C
36 lines
738 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_MT7620_RESET_H_
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#define _DT_BINDINGS_MT7620_RESET_H_
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#define PPE_RST 31
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#define SDHC_RST 30
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#define MIPS_CNT_RST 28
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#define PCIE_RST 26
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#define UHST_RST 25
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#define EPHY_RST 24
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#define ESW_RST 23
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#define UDEV_RST 22
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#define FE_RST 21
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#define WLAN_RST 20
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#define UARTL_RST 19
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#define SPI_RST 18
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#define I2S_RST 17
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#define I2C_RST 16
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#define NAND_RST 15
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#define DMA_RST 14
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#define PIO_RST 13
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#define UARTF_RST 12
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#define PCM_RST 11
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#define MC_RST 10
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#define INTC_RST 9
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#define TIMER_RST 8
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#define SYS_RST 0
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#endif /* _DT_BINDINGS_MT7620_RESET_H_ */
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