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https://github.com/brain-hackers/u-boot-brain
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6300dc4c61
Add support for the reset controller that's used on the i.MX7D and i.MX8MQ. This will be needed to be able to assert the PCIe reset pins. Bindings taken from Linux, driver implementation mostly taken from Linux and adjusted to U-Boot infrastructure. Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Fabio Estevam <festevam@gmail.com>
53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2017 Impinj, Inc.
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*
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* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
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*/
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#ifndef DT_BINDING_RESET_IMX7_H
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#define DT_BINDING_RESET_IMX7_H
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#define IMX7_RESET_A7_CORE_POR_RESET0 0
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#define IMX7_RESET_A7_CORE_POR_RESET1 1
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#define IMX7_RESET_A7_CORE_RESET0 2
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#define IMX7_RESET_A7_CORE_RESET1 3
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#define IMX7_RESET_A7_DBG_RESET0 4
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#define IMX7_RESET_A7_DBG_RESET1 5
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#define IMX7_RESET_A7_ETM_RESET0 6
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#define IMX7_RESET_A7_ETM_RESET1 7
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#define IMX7_RESET_A7_SOC_DBG_RESET 8
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#define IMX7_RESET_A7_L2RESET 9
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#define IMX7_RESET_SW_M4C_RST 10
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#define IMX7_RESET_SW_M4P_RST 11
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#define IMX7_RESET_EIM_RST 12
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#define IMX7_RESET_HSICPHY_PORT_RST 13
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#define IMX7_RESET_USBPHY1_POR 14
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#define IMX7_RESET_USBPHY1_PORT_RST 15
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#define IMX7_RESET_USBPHY2_POR 16
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#define IMX7_RESET_USBPHY2_PORT_RST 17
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#define IMX7_RESET_MIPI_PHY_MRST 18
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#define IMX7_RESET_MIPI_PHY_SRST 19
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/*
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* IMX7_RESET_PCIEPHY is a logical reset line combining PCIEPHY_BTN
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* and PCIEPHY_G_RST
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*/
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#define IMX7_RESET_PCIEPHY 20
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#define IMX7_RESET_PCIEPHY_PERST 21
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/*
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* IMX7_RESET_PCIE_CTRL_APPS_EN is not strictly a reset line, but it
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* can be used to inhibit PCIe LTTSM, so, in a way, it can be thoguht
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* of as one
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*/
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#define IMX7_RESET_PCIE_CTRL_APPS_EN 22
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#define IMX7_RESET_DDRC_PRST 23
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#define IMX7_RESET_DDRC_CORE_RST 24
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#define IMX7_RESET_PCIE_CTRL_APPS_TURNOFF 25
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#define IMX7_RESET_NUM 26
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#endif
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