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https://github.com/brain-hackers/u-boot-brain
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79c7a90f6c
This controller was introduced on Tegra114 to handle XUSB pads. On Tegra124 it is also used for PCIe and SATA pin muxing and PHY control. Only the Tegra124 PCIe and SATA functionality is currently implemented, with weak symbols on Tegra114. Tegra20 and Tegra30 also provide weak symbols for these functions so that drivers can use the same API irrespective of which SoC they're being built for. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
8 lines
201 B
C
8 lines
201 B
C
#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H
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#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1
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#define TEGRA_XUSB_PADCTL_PCIE 0
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#define TEGRA_XUSB_PADCTL_SATA 1
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#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */
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