mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
83 lines
2.0 KiB
C
83 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* Intel Quark MRC bindings include several properties
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* as part of an Intel Quark MRC node. In most cases,
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* the value of these properties uses the standard values
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* defined in this header.
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*/
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#ifndef _DT_BINDINGS_QRK_MRC_H_
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#define _DT_BINDINGS_QRK_MRC_H_
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/* MRC platform data flags */
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#define MRC_FLAG_ECC_EN 0x00000001
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#define MRC_FLAG_SCRAMBLE_EN 0x00000002
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#define MRC_FLAG_MEMTEST_EN 0x00000004
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/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
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#define MRC_FLAG_TOP_TREE_EN 0x00000008
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/* If set ODR signal is asserted to DRAM devices on writes */
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#define MRC_FLAG_WR_ODT_EN 0x00000010
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/* DRAM width */
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#define DRAM_WIDTH_X8 0
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#define DRAM_WIDTH_X16 1
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#define DRAM_WIDTH_X32 2
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/* DRAM speed */
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#define DRAM_FREQ_800 0
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#define DRAM_FREQ_1066 1
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/* DRAM type */
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#define DRAM_TYPE_DDR3 0
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#define DRAM_TYPE_DDR3L 1
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/* DRAM rank mask */
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#define DRAM_RANK(n) (1 << (n))
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/* DRAM channel mask */
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#define DRAM_CHANNEL(n) (1 << (n))
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/* DRAM channel width */
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#define DRAM_CHANNEL_WIDTH_X8 0
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#define DRAM_CHANNEL_WIDTH_X16 1
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#define DRAM_CHANNEL_WIDTH_X32 2
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/* DRAM address mode */
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#define DRAM_ADDR_MODE0 0
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#define DRAM_ADDR_MODE1 1
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#define DRAM_ADDR_MODE2 2
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/* DRAM refresh rate */
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#define DRAM_REFRESH_RATE_195US 1
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#define DRAM_REFRESH_RATE_39US 2
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#define DRAM_REFRESH_RATE_785US 3
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/* DRAM SR temprature range */
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#define DRAM_SRT_RANGE_NORMAL 0
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#define DRAM_SRT_RANGE_EXTENDED 1
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/* DRAM ron value */
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#define DRAM_RON_34OHM 0
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#define DRAM_RON_40OHM 1
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/* DRAM rtt nom value */
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#define DRAM_RTT_NOM_40OHM 0
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#define DRAM_RTT_NOM_60OHM 1
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#define DRAM_RTT_NOM_120OHM 2
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/* DRAM rd odt value */
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#define DRAM_RD_ODT_OFF 0
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#define DRAM_RD_ODT_60OHM 1
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#define DRAM_RD_ODT_120OHM 2
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#define DRAM_RD_ODT_180OHM 3
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/* DRAM density */
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#define DRAM_DENSITY_512M 0
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#define DRAM_DENSITY_1G 1
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#define DRAM_DENSITY_2G 2
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#define DRAM_DENSITY_4G 3
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#endif /* _DT_BINDINGS_QRK_MRC_H_ */
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