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403e9cbcd5
This adds a DRAM controller driver for the RK3368 and places it in drivers/ram/rockchip (where the other DM-enabled DRAM controller drivers for rockchip devices should also be moved eventually). At this stage, only the following feature-set is supported: - DDR3 - 32-bit configuration (i.e. fully populated) - dual-rank (i.e. no auto-detection of ranks) - DDR3-1600K speed-bin This driver expects to run from a TPL stage that will later return to the RK3368 BROM. It communicates with later stages through the os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR init code). Unlike other DMC drivers for RK32xx and RK33xx parts, the required timings are calculated within the driver based on a target frequency and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this time). The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0) register for controlling the operation of its (single-channel) DRAM controller in the GRF block. This provides for selecting DDR3, mobile DDR modes, and control low-power operation. As part of this change, DDRC0_CON0 is also added to the GRF structure definition (at offset 0x600). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
31 lines
622 B
C
31 lines
622 B
C
#ifndef DT_BINDINGS_RK3368_DMC_H
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#define DT_BINDINGS_RK3368_DMC_H
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#define DMC_MSCH_CBDR 0x0
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#define DMC_MSCH_CBRD 0x1
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#define DMC_MSCH_CRBD 0x2
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#define DDR3_800D 0
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#define DDR3_800E 1
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#define DDR3_1066E 2
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#define DDR3_1066F 3
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#define DDR3_1066G 4
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#define DDR3_1333F 5
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#define DDR3_1333G 6
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#define DDR3_1333H 7
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#define DDR3_1333J 8
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#define DDR3_1600G 9
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#define DDR3_1600H 10
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#define DDR3_1600J 11
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#define DDR3_1600K 12
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#define DDR3_1866J 13
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#define DDR3_1866K 14
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#define DDR3_1866L 15
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#define DDR3_1866M 16
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#define DDR3_2133K 17
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#define DDR3_2133L 18
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#define DDR3_2133M 19
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#define DDR3_2133N 20
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#endif
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