mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
60 lines
1.7 KiB
C
60 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION.
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*
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* This header provides constants for binding nvidia,tegra186-gpio*.
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*
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* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
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* provide names for this.
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*
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* The second cell contains standard flag values specified in gpio.h.
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*/
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#ifndef _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
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#define _DT_BINDINGS_GPIO_TEGRA186_GPIO_H
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#include <dt-bindings/gpio/gpio.h>
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/* GPIOs implemented by main GPIO controller */
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#define TEGRA_MAIN_GPIO_PORT_A 0
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#define TEGRA_MAIN_GPIO_PORT_B 1
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#define TEGRA_MAIN_GPIO_PORT_C 2
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#define TEGRA_MAIN_GPIO_PORT_D 3
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#define TEGRA_MAIN_GPIO_PORT_E 4
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#define TEGRA_MAIN_GPIO_PORT_F 5
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#define TEGRA_MAIN_GPIO_PORT_G 6
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#define TEGRA_MAIN_GPIO_PORT_H 7
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#define TEGRA_MAIN_GPIO_PORT_I 8
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#define TEGRA_MAIN_GPIO_PORT_J 9
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#define TEGRA_MAIN_GPIO_PORT_K 10
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#define TEGRA_MAIN_GPIO_PORT_L 11
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#define TEGRA_MAIN_GPIO_PORT_M 12
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#define TEGRA_MAIN_GPIO_PORT_N 13
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#define TEGRA_MAIN_GPIO_PORT_O 14
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#define TEGRA_MAIN_GPIO_PORT_P 15
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#define TEGRA_MAIN_GPIO_PORT_Q 16
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#define TEGRA_MAIN_GPIO_PORT_R 17
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#define TEGRA_MAIN_GPIO_PORT_T 18
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#define TEGRA_MAIN_GPIO_PORT_X 19
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#define TEGRA_MAIN_GPIO_PORT_Y 20
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#define TEGRA_MAIN_GPIO_PORT_BB 21
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#define TEGRA_MAIN_GPIO_PORT_CC 22
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#define TEGRA_MAIN_GPIO(port, offset) \
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((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
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/* GPIOs implemented by AON GPIO controller */
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#define TEGRA_AON_GPIO_PORT_S 0
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#define TEGRA_AON_GPIO_PORT_U 1
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#define TEGRA_AON_GPIO_PORT_V 2
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#define TEGRA_AON_GPIO_PORT_W 3
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#define TEGRA_AON_GPIO_PORT_Z 4
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#define TEGRA_AON_GPIO_PORT_AA 5
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#define TEGRA_AON_GPIO_PORT_EE 6
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#define TEGRA_AON_GPIO_PORT_FF 7
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#define TEGRA_AON_GPIO(port, offset) \
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((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
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#endif
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