mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
285 lines
8.0 KiB
C
285 lines
8.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*
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*/
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#ifndef _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
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#define _DT_BINDINGS_CLOCK_STM32MP1_CLKSRC_H_
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/* PLL output is enable when x=1, with x=p,q or r */
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#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2))
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/* st,clksrc: mandatory clock source */
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#define CLK_MPU_HSI 0x00000200
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#define CLK_MPU_HSE 0x00000201
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#define CLK_MPU_PLL1P 0x00000202
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#define CLK_MPU_PLL1P_DIV 0x00000203
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#define CLK_AXI_HSI 0x00000240
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#define CLK_AXI_HSE 0x00000241
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#define CLK_AXI_PLL2P 0x00000242
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#define CLK_MCU_HSI 0x00000480
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#define CLK_MCU_HSE 0x00000481
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#define CLK_MCU_CSI 0x00000482
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#define CLK_MCU_PLL3P 0x00000483
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#define CLK_PLL12_HSI 0x00000280
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#define CLK_PLL12_HSE 0x00000281
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#define CLK_PLL3_HSI 0x00008200
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#define CLK_PLL3_HSE 0x00008201
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#define CLK_PLL3_CSI 0x00008202
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#define CLK_PLL4_HSI 0x00008240
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#define CLK_PLL4_HSE 0x00008241
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#define CLK_PLL4_CSI 0x00008242
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#define CLK_PLL4_I2SCKIN 0x00008243
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#define CLK_RTC_DISABLED 0x00001400
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#define CLK_RTC_LSE 0x00001401
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#define CLK_RTC_LSI 0x00001402
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#define CLK_RTC_HSE 0x00001403
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#define CLK_MCO1_HSI 0x00008000
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#define CLK_MCO1_HSE 0x00008001
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#define CLK_MCO1_CSI 0x00008002
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#define CLK_MCO1_LSI 0x00008003
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#define CLK_MCO1_LSE 0x00008004
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#define CLK_MCO1_DISABLED 0x0000800F
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#define CLK_MCO2_MPU 0x00008040
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#define CLK_MCO2_AXI 0x00008041
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#define CLK_MCO2_MCU 0x00008042
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#define CLK_MCO2_PLL4P 0x00008043
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#define CLK_MCO2_HSE 0x00008044
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#define CLK_MCO2_HSI 0x00008045
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#define CLK_MCO2_DISABLED 0x0000804F
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/* st,pkcs: peripheral kernel clock source */
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#define CLK_I2C12_PCLK1 0x00008C00
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#define CLK_I2C12_PLL4R 0x00008C01
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#define CLK_I2C12_HSI 0x00008C02
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#define CLK_I2C12_CSI 0x00008C03
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#define CLK_I2C12_DISABLED 0x00008C07
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#define CLK_I2C35_PCLK1 0x00008C40
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#define CLK_I2C35_PLL4R 0x00008C41
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#define CLK_I2C35_HSI 0x00008C42
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#define CLK_I2C35_CSI 0x00008C43
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#define CLK_I2C35_DISABLED 0x00008C47
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#define CLK_I2C46_PCLK5 0x00000C00
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#define CLK_I2C46_PLL3Q 0x00000C01
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#define CLK_I2C46_HSI 0x00000C02
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#define CLK_I2C46_CSI 0x00000C03
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#define CLK_I2C46_DISABLED 0x00000C07
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#define CLK_SAI1_PLL4Q 0x00008C80
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#define CLK_SAI1_PLL3Q 0x00008C81
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#define CLK_SAI1_I2SCKIN 0x00008C82
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#define CLK_SAI1_CKPER 0x00008C83
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#define CLK_SAI1_PLL3R 0x00008C84
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#define CLK_SAI1_DISABLED 0x00008C87
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#define CLK_SAI2_PLL4Q 0x00008CC0
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#define CLK_SAI2_PLL3Q 0x00008CC1
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#define CLK_SAI2_I2SCKIN 0x00008CC2
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#define CLK_SAI2_CKPER 0x00008CC3
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#define CLK_SAI2_SPDIF 0x00008CC4
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#define CLK_SAI2_PLL3R 0x00008CC5
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#define CLK_SAI2_DISABLED 0x00008CC7
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#define CLK_SAI3_PLL4Q 0x00008D00
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#define CLK_SAI3_PLL3Q 0x00008D01
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#define CLK_SAI3_I2SCKIN 0x00008D02
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#define CLK_SAI3_CKPER 0x00008D03
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#define CLK_SAI3_PLL3R 0x00008D04
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#define CLK_SAI3_DISABLED 0x00008D07
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#define CLK_SAI4_PLL4Q 0x00008D40
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#define CLK_SAI4_PLL3Q 0x00008D41
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#define CLK_SAI4_I2SCKIN 0x00008D42
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#define CLK_SAI4_CKPER 0x00008D43
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#define CLK_SAI4_PLL3R 0x00008D44
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#define CLK_SAI4_DISABLED 0x00008D47
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#define CLK_SPI2S1_PLL4P 0x00008D80
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#define CLK_SPI2S1_PLL3Q 0x00008D81
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#define CLK_SPI2S1_I2SCKIN 0x00008D82
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#define CLK_SPI2S1_CKPER 0x00008D83
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#define CLK_SPI2S1_PLL3R 0x00008D84
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#define CLK_SPI2S1_DISABLED 0x00008D87
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#define CLK_SPI2S23_PLL4P 0x00008DC0
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#define CLK_SPI2S23_PLL3Q 0x00008DC1
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#define CLK_SPI2S23_I2SCKIN 0x00008DC2
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#define CLK_SPI2S23_CKPER 0x00008DC3
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#define CLK_SPI2S23_PLL3R 0x00008DC4
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#define CLK_SPI2S23_DISABLED 0x00008DC7
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#define CLK_SPI45_PCLK2 0x00008E00
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#define CLK_SPI45_PLL4Q 0x00008E01
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#define CLK_SPI45_HSI 0x00008E02
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#define CLK_SPI45_CSI 0x00008E03
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#define CLK_SPI45_HSE 0x00008E04
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#define CLK_SPI45_DISABLED 0x00008E07
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#define CLK_SPI6_PCLK5 0x00000C40
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#define CLK_SPI6_PLL4Q 0x00000C41
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#define CLK_SPI6_HSI 0x00000C42
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#define CLK_SPI6_CSI 0x00000C43
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#define CLK_SPI6_HSE 0x00000C44
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#define CLK_SPI6_PLL3Q 0x00000C45
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#define CLK_SPI6_DISABLED 0x00000C47
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#define CLK_UART6_PCLK2 0x00008E40
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#define CLK_UART6_PLL4Q 0x00008E41
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#define CLK_UART6_HSI 0x00008E42
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#define CLK_UART6_CSI 0x00008E43
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#define CLK_UART6_HSE 0x00008E44
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#define CLK_UART6_DISABLED 0x00008E47
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#define CLK_UART24_PCLK1 0x00008E80
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#define CLK_UART24_PLL4Q 0x00008E81
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#define CLK_UART24_HSI 0x00008E82
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#define CLK_UART24_CSI 0x00008E83
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#define CLK_UART24_HSE 0x00008E84
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#define CLK_UART24_DISABLED 0x00008E87
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#define CLK_UART35_PCLK1 0x00008EC0
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#define CLK_UART35_PLL4Q 0x00008EC1
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#define CLK_UART35_HSI 0x00008EC2
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#define CLK_UART35_CSI 0x00008EC3
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#define CLK_UART35_HSE 0x00008EC4
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#define CLK_UART35_DISABLED 0x00008EC7
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#define CLK_UART78_PCLK1 0x00008F00
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#define CLK_UART78_PLL4Q 0x00008F01
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#define CLK_UART78_HSI 0x00008F02
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#define CLK_UART78_CSI 0x00008F03
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#define CLK_UART78_HSE 0x00008F04
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#define CLK_UART78_DISABLED 0x00008F07
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#define CLK_UART1_PCLK5 0x00000C80
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#define CLK_UART1_PLL3Q 0x00000C81
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#define CLK_UART1_HSI 0x00000C82
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#define CLK_UART1_CSI 0x00000C83
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#define CLK_UART1_PLL4Q 0x00000C84
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#define CLK_UART1_HSE 0x00000C85
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#define CLK_UART1_DISABLED 0x00000C87
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#define CLK_SDMMC12_HCLK6 0x00008F40
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#define CLK_SDMMC12_PLL3R 0x00008F41
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#define CLK_SDMMC12_PLL4P 0x00008F42
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#define CLK_SDMMC12_HSI 0x00008F43
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#define CLK_SDMMC12_DISABLED 0x00008F47
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#define CLK_SDMMC3_HCLK2 0x00008F80
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#define CLK_SDMMC3_PLL3R 0x00008F81
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#define CLK_SDMMC3_PLL4P 0x00008F82
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#define CLK_SDMMC3_HSI 0x00008F83
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#define CLK_SDMMC3_DISABLED 0x00008F87
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#define CLK_ETH_PLL4P 0x00008FC0
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#define CLK_ETH_PLL3Q 0x00008FC1
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#define CLK_ETH_DISABLED 0x00008FC3
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#define CLK_QSPI_ACLK 0x00009000
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#define CLK_QSPI_PLL3R 0x00009001
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#define CLK_QSPI_PLL4P 0x00009002
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#define CLK_QSPI_CKPER 0x00009003
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#define CLK_FMC_ACLK 0x00009040
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#define CLK_FMC_PLL3R 0x00009041
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#define CLK_FMC_PLL4P 0x00009042
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#define CLK_FMC_CKPER 0x00009043
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#define CLK_FDCAN_HSE 0x000090C0
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#define CLK_FDCAN_PLL3Q 0x000090C1
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#define CLK_FDCAN_PLL4Q 0x000090C2
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#define CLK_FDCAN_PLL4R 0x000090C3
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#define CLK_SPDIF_PLL4P 0x00009140
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#define CLK_SPDIF_PLL3Q 0x00009141
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#define CLK_SPDIF_HSI 0x00009142
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#define CLK_SPDIF_DISABLED 0x00009143
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#define CLK_CEC_LSE 0x00009180
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#define CLK_CEC_LSI 0x00009181
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#define CLK_CEC_CSI_DIV122 0x00009182
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#define CLK_CEC_DISABLED 0x00009183
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#define CLK_USBPHY_HSE 0x000091C0
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#define CLK_USBPHY_PLL4R 0x000091C1
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#define CLK_USBPHY_HSE_DIV2 0x000091C2
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#define CLK_USBPHY_DISABLED 0x000091C3
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#define CLK_USBO_PLL4R 0x800091C0
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#define CLK_USBO_USBPHY 0x800091C1
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#define CLK_RNG1_CSI 0x00000CC0
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#define CLK_RNG1_PLL4R 0x00000CC1
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#define CLK_RNG1_LSE 0x00000CC2
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#define CLK_RNG1_LSI 0x00000CC3
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#define CLK_RNG2_CSI 0x00009200
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#define CLK_RNG2_PLL4R 0x00009201
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#define CLK_RNG2_LSE 0x00009202
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#define CLK_RNG2_LSI 0x00009203
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#define CLK_CKPER_HSI 0x00000D00
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#define CLK_CKPER_CSI 0x00000D01
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#define CLK_CKPER_HSE 0x00000D02
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#define CLK_CKPER_DISABLED 0x00000D03
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#define CLK_STGEN_HSI 0x00000D40
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#define CLK_STGEN_HSE 0x00000D41
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#define CLK_STGEN_DISABLED 0x00000D43
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#define CLK_DSI_DSIPLL 0x00009240
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#define CLK_DSI_PLL4P 0x00009241
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#define CLK_ADC_PLL4R 0x00009280
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#define CLK_ADC_CKPER 0x00009281
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#define CLK_ADC_PLL3Q 0x00009282
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#define CLK_ADC_DISABLED 0x00009283
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#define CLK_LPTIM45_PCLK3 0x000092C0
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#define CLK_LPTIM45_PLL4P 0x000092C1
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#define CLK_LPTIM45_PLL3Q 0x000092C2
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#define CLK_LPTIM45_LSE 0x000092C3
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#define CLK_LPTIM45_LSI 0x000092C4
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#define CLK_LPTIM45_CKPER 0x000092C5
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#define CLK_LPTIM45_DISABLED 0x000092C7
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#define CLK_LPTIM23_PCLK3 0x00009300
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#define CLK_LPTIM23_PLL4Q 0x00009301
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#define CLK_LPTIM23_CKPER 0x00009302
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#define CLK_LPTIM23_LSE 0x00009303
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#define CLK_LPTIM23_LSI 0x00009304
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#define CLK_LPTIM23_DISABLED 0x00009307
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#define CLK_LPTIM1_PCLK1 0x00009340
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#define CLK_LPTIM1_PLL4P 0x00009341
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#define CLK_LPTIM1_PLL3Q 0x00009342
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#define CLK_LPTIM1_LSE 0x00009343
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#define CLK_LPTIM1_LSI 0x00009344
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#define CLK_LPTIM1_CKPER 0x00009345
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#define CLK_LPTIM1_DISABLED 0x00009347
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/* define for st,pll /csg */
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#define SSCG_MODE_CENTER_SPREAD 0
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#define SSCG_MODE_DOWN_SPREAD 1
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/* define for st,drive */
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#define LSEDRV_LOWEST 0
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#define LSEDRV_MEDIUM_LOW 1
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#define LSEDRV_MEDIUM_HIGH 2
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#define LSEDRV_HIGHEST 3
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#endif
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