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9072400775
Add clock driver for MediaTek MT8518 SoC. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
250 lines
7.1 KiB
C
250 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _DT_BINDINGS_CLK_MT8518_H
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#define _DT_BINDINGS_CLK_MT8518_H
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/* APMIXEDSYS */
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#define CLK_APMIXED_ARMPLL 0
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#define CLK_APMIXED_MAINPLL 1
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#define CLK_APMIXED_UNIVPLL 2
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#define CLK_APMIXED_MMPLL 3
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#define CLK_APMIXED_APLL1 4
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#define CLK_APMIXED_APLL2 5
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#define CLK_APMIXED_TVDPLL 6
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#define CLK_APMIXED_NR_CLK 7
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/* TOPCKGEN */
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#define CLK_TOP_CLK_NULL 0
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#define CLK_TOP_FQ_TRNG_OUT0 1
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#define CLK_TOP_FQ_TRNG_OUT1 2
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#define CLK_TOP_CLK32K 3
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#define CLK_TOP_DMPLL 4
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#define CLK_TOP_MAINPLL_D4 5
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#define CLK_TOP_MAINPLL_D8 6
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#define CLK_TOP_MAINPLL_D16 7
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#define CLK_TOP_MAINPLL_D11 8
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#define CLK_TOP_MAINPLL_D22 9
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#define CLK_TOP_MAINPLL_D3 10
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#define CLK_TOP_MAINPLL_D6 11
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#define CLK_TOP_MAINPLL_D12 12
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#define CLK_TOP_MAINPLL_D5 13
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#define CLK_TOP_MAINPLL_D10 14
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#define CLK_TOP_MAINPLL_D20 15
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#define CLK_TOP_MAINPLL_D40 16
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#define CLK_TOP_MAINPLL_D7 17
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#define CLK_TOP_MAINPLL_D14 18
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#define CLK_TOP_UNIVPLL_D2 19
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#define CLK_TOP_UNIVPLL_D4 20
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#define CLK_TOP_UNIVPLL_D8 21
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#define CLK_TOP_UNIVPLL_D16 22
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#define CLK_TOP_UNIVPLL_D3 23
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#define CLK_TOP_UNIVPLL_D6 24
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#define CLK_TOP_UNIVPLL_D12 25
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#define CLK_TOP_UNIVPLL_D24 26
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#define CLK_TOP_UNIVPLL_D5 27
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#define CLK_TOP_UNIVPLL_D20 28
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#define CLK_TOP_UNIVPLL_D10 29
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#define CLK_TOP_MMPLL_D2 30
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#define CLK_TOP_USB20_48M 31
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#define CLK_TOP_APLL1 32
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#define CLK_TOP_APLL1_D4 33
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#define CLK_TOP_APLL2 34
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#define CLK_TOP_APLL2_D2 35
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#define CLK_TOP_APLL2_D3 36
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#define CLK_TOP_APLL2_D4 37
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#define CLK_TOP_APLL2_D8 38
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#define CLK_TOP_CLK26M 39
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#define CLK_TOP_CLK26M_D2 40
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#define CLK_TOP_CLK26M_D4 41
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#define CLK_TOP_CLK26M_D8 42
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#define CLK_TOP_CLK26M_D793 43
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#define CLK_TOP_TVDPLL 44
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#define CLK_TOP_TVDPLL_D2 45
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#define CLK_TOP_TVDPLL_D4 46
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#define CLK_TOP_TVDPLL_D8 47
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#define CLK_TOP_TVDPLL_D16 48
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#define CLK_TOP_USB20_CLK480M 49
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#define CLK_TOP_RG_APLL1_D2 50
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#define CLK_TOP_RG_APLL1_D4 51
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#define CLK_TOP_RG_APLL1_D8 52
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#define CLK_TOP_RG_APLL1_D16 53
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#define CLK_TOP_RG_APLL1_D3 54
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#define CLK_TOP_RG_APLL2_D2 55
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#define CLK_TOP_RG_APLL2_D4 56
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#define CLK_TOP_RG_APLL2_D8 57
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#define CLK_TOP_RG_APLL2_D16 58
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#define CLK_TOP_RG_APLL2_D3 59
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#define CLK_TOP_NFI1X_INFRA_BCLK 60
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#define CLK_TOP_AHB_INFRA_D2 61
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#define CLK_TOP_UART0_SEL 62
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#define CLK_TOP_EMI1X_SEL 63
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#define CLK_TOP_EMI_DDRPHY_SEL 64
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#define CLK_TOP_MSDC1_SEL 65
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#define CLK_TOP_PWM_MM_SEL 66
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#define CLK_TOP_UART1_SEL 67
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#define CLK_TOP_SPM_52M_SEL 68
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#define CLK_TOP_PMICSPI_SEL 69
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#define CLK_TOP_NFI2X_SEL 70
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#define CLK_TOP_DDRPHYCFG_SEL 71
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#define CLK_TOP_SMI_SEL 72
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#define CLK_TOP_USB_SEL 73
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#define CLK_TOP_SPINOR_SEL 74
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#define CLK_TOP_ETH_SEL 75
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#define CLK_TOP_AUD1_SEL 76
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#define CLK_TOP_AUD2_SEL 77
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#define CLK_TOP_I2C_SEL 78
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#define CLK_TOP_AUD_I2S0_M_SEL 79
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#define CLK_TOP_AUD_I2S3_M_SEL 80
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#define CLK_TOP_AUD_I2S4_M_SEL 81
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#define CLK_TOP_AUD_I2S6_M_SEL 82
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#define CLK_TOP_PWM_SEL 83
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#define CLK_TOP_AUD_SPDIFIN_SEL 84
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#define CLK_TOP_UART2_SEL 85
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#define CLK_TOP_DBG_ATCLK_SEL 86
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#define CLK_TOP_PNG_SYS_SEL 87
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#define CLK_TOP_SEJ_13M_SEL 88
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#define CLK_TOP_IMGRZ_SYS_SEL 89
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#define CLK_TOP_GRAPH_ECLK_SEL 90
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#define CLK_TOP_FDBI_SEL 91
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#define CLK_TOP_FAUDIO_SEL 92
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#define CLK_TOP_FA2SYS_SEL 93
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#define CLK_TOP_FA1SYS_SEL 94
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#define CLK_TOP_FASM_M_SEL 95
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#define CLK_TOP_FASM_H_SEL 96
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#define CLK_TOP_FASM_L_SEL 97
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#define CLK_TOP_FECC_CK_SEL 98
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#define CLK_TOP_PE2_MAC_SEL 99
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#define CLK_TOP_CMSYS_SEL 100
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#define CLK_TOP_GCPU_SEL 101
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#define CLK_TOP_SPIS_CK_SEL 102
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#define CLK_TOP_APLL1_REF_SEL 103
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#define CLK_TOP_APLL2_REF_SEL 104
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#define CLK_TOP_INT_32K_SEL 105
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#define CLK_TOP_APLL1_SRC_SEL 106
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#define CLK_TOP_APLL2_SRC_SEL 107
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#define CLK_TOP_FAUD_INTBUS_SEL 108
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#define CLK_TOP_AXIBUS_SEL 109
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#define CLK_TOP_HAPLL1_SEL 110
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#define CLK_TOP_HAPLL2_SEL 111
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#define CLK_TOP_SPINFI_SEL 112
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#define CLK_TOP_MSDC0_SEL 113
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#define CLK_TOP_MSDC0_CLK50_SEL 114
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#define CLK_TOP_MSDC2_SEL 115
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#define CLK_TOP_MSDC2_CLK50_SEL 116
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#define CLK_TOP_DISP_DPI_CK_SEL 117
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#define CLK_TOP_SPI1_SEL 118
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#define CLK_TOP_SPI2_SEL 119
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#define CLK_TOP_SPI3_SEL 120
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#define CLK_TOP_APLL12_CK_DIV0 121
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#define CLK_TOP_APLL12_CK_DIV3 122
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#define CLK_TOP_APLL12_CK_DIV4 123
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#define CLK_TOP_APLL12_CK_DIV6 124
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/* TOPCKGEN Gates */
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#define CLK_TOP_PWM_MM 0
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#define CLK_TOP_SMI 1
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#define CLK_TOP_SPI2 2
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#define CLK_TOP_SPI3 3
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#define CLK_TOP_SPINFI 4
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#define CLK_TOP_26M_DEBUG 5
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#define CLK_TOP_USB_48M_DEBUG 6
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#define CLK_TOP_52M_DEBUG 7
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#define CLK_TOP_32K_DEBUG 8
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#define CLK_TOP_THERM 9
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#define CLK_TOP_APDMA 10
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#define CLK_TOP_I2C0 11
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#define CLK_TOP_I2C1 12
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#define CLK_TOP_AUXADC1 13
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#define CLK_TOP_NFI 14
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#define CLK_TOP_NFIECC 15
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#define CLK_TOP_DEBUGSYS 16
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#define CLK_TOP_PWM 17
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#define CLK_TOP_UART0 18
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#define CLK_TOP_UART1 19
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#define CLK_TOP_USB 20
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#define CLK_TOP_FLASHIF_26M 21
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#define CLK_TOP_AUXADC2 22
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#define CLK_TOP_I2C2 23
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#define CLK_TOP_MSDC0 24
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#define CLK_TOP_MSDC1 25
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#define CLK_TOP_NFI2X 26
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#define CLK_TOP_MEMSLP_DLYER 27
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#define CLK_TOP_SPI 28
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#define CLK_TOP_APXGPT 29
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#define CLK_TOP_PMICWRAP_MD 30
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#define CLK_TOP_PMICWRAP_CONN 31
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#define CLK_TOP_PMIC_SYSCK 32
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#define CLK_TOP_AUX_ADC 33
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#define CLK_TOP_AUX_TP 34
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#define CLK_TOP_RBIST 35
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#define CLK_TOP_NFI_BUS 36
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#define CLK_TOP_GCE 37
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#define CLK_TOP_TRNG 38
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#define CLK_TOP_PWM_B 39
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#define CLK_TOP_PWM1_FB 40
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#define CLK_TOP_PWM2_FB 41
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#define CLK_TOP_PWM3_FB 42
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#define CLK_TOP_PWM4_FB 43
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#define CLK_TOP_PWM5_FB 44
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#define CLK_TOP_FLASHIF_FREERUN 45
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#define CLK_TOP_CQDMA 46
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#define CLK_TOP_66M_ETH 47
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#define CLK_TOP_133M_ETH 48
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#define CLK_TOP_FLASHIF_AXI 49
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#define CLK_TOP_USBIF 50
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#define CLK_TOP_UART2 51
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#define CLK_TOP_GCPU_B 52
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#define CLK_TOP_MSDC0_B 53
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#define CLK_TOP_MSDC1_B 54
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#define CLK_TOP_MSDC2_B 55
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#define CLK_TOP_USB_B 56
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#define CLK_TOP_SPINOR 57
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#define CLK_TOP_MSDC2 58
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#define CLK_TOP_ETH 59
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#define CLK_TOP_AUD1 60
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#define CLK_TOP_AUD2 61
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#define CLK_TOP_I2C 62
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#define CLK_TOP_PWM_INFRA 63
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#define CLK_TOP_AUD_SPDIF_IN 64
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#define CLK_TOP_RG_UART2 65
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#define CLK_TOP_DBG_AT 66
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#define CLK_TOP_APLL12_DIV0 67
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#define CLK_TOP_APLL12_DIV3 68
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#define CLK_TOP_APLL12_DIV4 69
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#define CLK_TOP_APLL12_DIV6 70
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#define CLK_TOP_IMGRZ_SYS 71
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#define CLK_TOP_PNG_SYS 72
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#define CLK_TOP_GRAPH_E 73
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#define CLK_TOP_FDBI 74
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#define CLK_TOP_FAUDIO 75
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#define CLK_TOP_FAUD_INTBUS 76
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#define CLK_TOP_HAPLL1 77
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#define CLK_TOP_HAPLL2 78
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#define CLK_TOP_FA2SYS 79
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#define CLK_TOP_FA1SYS 80
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#define CLK_TOP_FASM_L 81
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#define CLK_TOP_FASM_M 82
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#define CLK_TOP_FASM_H 83
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#define CLK_TOP_FECC 84
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#define CLK_TOP_PE2_MAC 85
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#define CLK_TOP_CMSYS 86
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#define CLK_TOP_GCPU 87
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#define CLK_TOP_SPIS 88
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#define CLK_TOP_I2C3 89
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#define CLK_TOP_SPI_SLV_B 90
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#define CLK_TOP_SPI_SLV_BUS 91
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#define CLK_TOP_PCIE_MAC_BUS 92
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#define CLK_TOP_CMSYS_BUS 93
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#define CLK_TOP_ECC_B 94
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#define CLK_TOP_PCIE_PHY_BUS 95
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#define CLK_TOP_PCIE_AUX 96
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#define CLK_TOP_DISP_DPI 97
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#define CLK_TOP_NR_CLK 98
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#endif /* _DT_BINDINGS_CLK_MT8518_H */
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