53 lines
1.7 KiB
C
53 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright(C) 2020
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* Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMXRT1020_H
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#define __DT_BINDINGS_CLOCK_IMXRT1020_H
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#define IMXRT1020_CLK_DUMMY 0
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#define IMXRT1020_CLK_CKIL 1
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#define IMXRT1020_CLK_CKIH 2
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#define IMXRT1020_CLK_OSC 3
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#define IMXRT1020_CLK_PLL2_PFD0_352M 4
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#define IMXRT1020_CLK_PLL2_PFD1_594M 5
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#define IMXRT1020_CLK_PLL2_PFD2_396M 6
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#define IMXRT1020_CLK_PLL2_PFD3_297M 7
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#define IMXRT1020_CLK_PLL3_PFD0_720M 8
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#define IMXRT1020_CLK_PLL3_PFD1_664_62M 9
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#define IMXRT1020_CLK_PLL3_PFD2_508_24M 10
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#define IMXRT1020_CLK_PLL3_PFD3_454_74M 11
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#define IMXRT1020_CLK_PLL2_198M 12
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#define IMXRT1020_CLK_PLL3_120M 13
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#define IMXRT1020_CLK_PLL3_80M 14
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#define IMXRT1020_CLK_PLL3_60M 15
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#define IMXRT1020_CLK_PLL2_BYPASS 16
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#define IMXRT1020_CLK_PLL3_BYPASS 17
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#define IMXRT1020_CLK_PLL6_BYPASS 18
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#define IMXRT1020_CLK_PRE_PERIPH_SEL 19
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#define IMXRT1020_CLK_PERIPH_SEL 20
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#define IMXRT1020_CLK_SEMC_ALT_SEL 21
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#define IMXRT1020_CLK_SEMC_SEL 22
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#define IMXRT1020_CLK_USDHC1_SEL 23
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#define IMXRT1020_CLK_USDHC2_SEL 24
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#define IMXRT1020_CLK_LPUART_SEL 25
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#define IMXRT1020_CLK_ARM_PODF 26
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#define IMXRT1020_CLK_LPUART_PODF 27
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#define IMXRT1020_CLK_USDHC1_PODF 28
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#define IMXRT1020_CLK_USDHC2_PODF 29
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#define IMXRT1020_CLK_SEMC_PODF 30
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#define IMXRT1020_CLK_AHB_PODF 31
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#define IMXRT1020_CLK_USDHC1 32
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#define IMXRT1020_CLK_USDHC2 33
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#define IMXRT1020_CLK_LPUART1 34
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#define IMXRT1020_CLK_SEMC 35
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#define IMXRT1020_CLK_PLL2_SYS 36
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#define IMXRT1020_CLK_PLL3_USB_OTG 37
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#define IMXRT1020_CLK_PLL4_AUDIO 38
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#define IMXRT1020_CLK_PLL6_ENET 39
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#define IMXRT1020_CLK_END 40
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#endif /* __DT_BINDINGS_CLOCK_IMXRT1020_H */
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