107 lines
2.9 KiB
C
107 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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#ifndef __PHYCORE_IMX8MP_H
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#define __PHYCORE_IMX8MP_H
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#include <linux/sizes.h>
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#include <asm/arch/imx-regs.h>
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#define CONFIG_SYS_BOOTM_LEN SZ_64M
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#define CONFIG_SPL_MAX_SIZE (152 * SZ_1K)
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#define CONFIG_SYS_MONITOR_LEN SZ_512K
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
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#define CONFIG_SYS_UBOOT_BASE \
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(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
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#define CONFIG_SPL_STACK 0x960000
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#define CONFIG_SPL_BSS_START_ADDR 0x98FC00
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#define CONFIG_SPL_BSS_MAX_SIZE SZ_1K
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#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#define CONFIG_POWER
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#define CONFIG_POWER_I2C
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#define CONFIG_POWER_PCA9450
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#define CONFIG_SYS_I2C
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#endif
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"image=Image\0" \
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"console=ttymxc1,115200\0" \
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"fdt_addr=0x48000000\0" \
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"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
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"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
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"mmcroot=2\0" \
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"mmcautodetect=yes\0" \
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"mmcargs=setenv bootargs console=${console} " \
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"root=/dev/mmcblk${mmcdev}p${mmcroot} rootwait rw\0" \
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"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
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"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"if run loadfdt; then " \
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"booti ${loadaddr} - ${fdt_addr}; " \
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"else " \
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"echo WARN: Cannot load the DT; " \
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"fi;\0 " \
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadimage; then " \
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"run mmcboot; " \
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"else run netboot; " \
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"fi; " \
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"fi;"
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/* Link Definitions */
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#define CONFIG_LOADADDR 0x40480000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN SZ_32M
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE 0x80000000
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/* UART */
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#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE SZ_2K
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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/* USDHC */
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#define CONFIG_FSL_USDHC
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
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/* I2C */
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#define CONFIG_SYS_I2C_SPEED 100000
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#endif /* __PHYCORE_IMX8MP_H */
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