126 lines
3.3 KiB
C
126 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2019 NXP
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*/
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#ifndef __IMX8MP_EVK_H
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#define __IMX8MP_EVK_H
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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#include <asm/arch/imx-regs.h>
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#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
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#define CONFIG_SPL_MAX_SIZE (152 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
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#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
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#ifdef CONFIG_SPL_BUILD
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/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
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#define CONFIG_SPL_STACK 0x960000
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#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00
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#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */
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#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
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#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
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#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
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#undef CONFIG_DM_MMC
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#undef CONFIG_DM_PMIC
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#undef CONFIG_DM_PMIC_PFUZE100
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#define CONFIG_POWER
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#define CONFIG_POWER_I2C
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#define CONFIG_POWER_PCA9450
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#define CONFIG_SYS_I2C
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#endif
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#if defined(CONFIG_CMD_NET)
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#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_FEC_MXC_PHYADDR 1
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#define FEC_QUIRK_ENET_MAC
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#define DWC_NET_PHYADDR 1
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#ifdef CONFIG_DWC_ETH_QOS
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#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
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#endif
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#define PHY_ANEG_TIMEOUT 20000
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#endif
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#ifndef CONFIG_SPL_BUILD
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 1) \
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func(MMC, mmc, 2)
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#include <config_distro_bootcmd.h>
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#endif
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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BOOTENV \
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"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
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"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
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"image=Image\0" \
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"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
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"fdt_addr_r=0x43000000\0" \
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"boot_fdt=try\0" \
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"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
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"initrd_addr=0x43800000\0" \
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"bootm_size=0x10000000\0" \
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"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
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"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
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/* Link Definitions */
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#define CONFIG_LOADADDR 0x40480000
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
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#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN SZ_32M
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/* Totally 6GB DDR */
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define PHYS_SDRAM 0x40000000
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#define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */
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#define PHYS_SDRAM_2 0x100000000
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#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */
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#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 2048
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#define CONFIG_SYS_MAXARGS 64
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_FSL_USDHC
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
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#define CONFIG_SYS_I2C_SPEED 100000
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#endif
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