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https://github.com/brain-hackers/u-boot-brain
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e09b88cd08
This patch adds support for the MediaTek USB3 DRD controller, its host side is based on xHCI, this driver supports device mode and host mode. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
142 lines
3.6 KiB
C
142 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* mtu3_dr.c - dual role switch and host glue layer
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*
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* Copyright (C) 2016 MediaTek Inc.
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*
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* Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
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*/
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#include <dm/lists.h>
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#include <linux/iopoll.h>
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#include "mtu3.h"
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#include "mtu3_dr.h"
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static void host_ports_num_get(struct mtu3_host *u3h)
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{
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u32 xhci_cap;
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xhci_cap = mtu3_readl(u3h->ippc_base, U3D_SSUSB_IP_XHCI_CAP);
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u3h->u2_ports = SSUSB_IP_XHCI_U2_PORT_NUM(xhci_cap);
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u3h->u3_ports = SSUSB_IP_XHCI_U3_PORT_NUM(xhci_cap);
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dev_dbg(u3h->dev, "host - u2_ports:%d, u3_ports:%d\n",
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u3h->u2_ports, u3h->u3_ports);
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}
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/* only configure ports will be used later */
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static int ssusb_host_enable(struct mtu3_host *u3h)
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{
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void __iomem *ibase = u3h->ippc_base;
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int num_u3p = u3h->u3_ports;
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int num_u2p = u3h->u2_ports;
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int u3_ports_disabed;
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u32 check_clk;
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u32 value;
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int i;
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/* power on host ip */
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mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
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/* power on and enable u3 ports except skipped ones */
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u3_ports_disabed = 0;
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for (i = 0; i < num_u3p; i++) {
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if ((0x1 << i) & u3h->u3p_dis_msk) {
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u3_ports_disabed++;
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continue;
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}
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value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
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value &= ~(SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS);
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value |= SSUSB_U3_PORT_HOST_SEL;
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mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
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}
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/* power on and enable all u2 ports */
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for (i = 0; i < num_u2p; i++) {
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value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
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value &= ~(SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_DIS);
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value |= SSUSB_U2_PORT_HOST_SEL;
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mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
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}
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check_clk = SSUSB_XHCI_RST_B_STS;
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if (num_u3p > u3_ports_disabed)
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check_clk = SSUSB_U3_MAC_RST_B_STS;
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return ssusb_check_clocks(u3h->ssusb, check_clk);
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}
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static void ssusb_host_disable(struct mtu3_host *u3h)
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{
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void __iomem *ibase = u3h->ippc_base;
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int num_u3p = u3h->u3_ports;
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int num_u2p = u3h->u2_ports;
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u32 value;
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int i;
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/* power down and disable u3 ports except skipped ones */
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for (i = 0; i < num_u3p; i++) {
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if ((0x1 << i) & u3h->u3p_dis_msk)
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continue;
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value = mtu3_readl(ibase, SSUSB_U3_CTRL(i));
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value |= SSUSB_U3_PORT_PDN | SSUSB_U3_PORT_DIS;
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mtu3_writel(ibase, SSUSB_U3_CTRL(i), value);
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}
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/* power down and disable all u2 ports */
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for (i = 0; i < num_u2p; i++) {
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value = mtu3_readl(ibase, SSUSB_U2_CTRL(i));
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value |= SSUSB_U2_PORT_PDN | SSUSB_U2_PORT_DIS;
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mtu3_writel(ibase, SSUSB_U2_CTRL(i), value);
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}
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/* power down host ip */
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mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL1, SSUSB_IP_HOST_PDN);
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}
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/*
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* If host supports multiple ports, the VBUSes(5V) of ports except port0
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* which supports OTG are better to be enabled by default in DTS.
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* Because the host driver will keep link with devices attached when system
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* enters suspend mode, so no need to control VBUSes after initialization.
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*/
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int ssusb_host_init(struct ssusb_mtk *ssusb)
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{
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struct mtu3_host *u3h = ssusb->u3h;
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struct udevice *dev = u3h->dev;
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int ret;
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u3h->ssusb = ssusb;
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u3h->hcd = ssusb->mac_base;
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u3h->ippc_base = ssusb->ippc_base;
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/* optional property, ignore the error */
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dev_read_u32(dev, "mediatek,u3p-dis-msk", &u3h->u3p_dis_msk);
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host_ports_num_get(u3h);
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ret = ssusb_host_enable(u3h);
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if (ret)
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return ret;
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ssusb_set_force_mode(ssusb, MTU3_DR_FORCE_HOST);
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ret = regulator_set_enable(ssusb->vbus_supply, true);
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if (ret < 0 && ret != -ENOSYS) {
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dev_err(dev, "failed to enable vbus %d!\n", ret);
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return ret;
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}
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dev_info(dev, "%s done...\n", __func__);
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return 0;
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}
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void ssusb_host_exit(struct ssusb_mtk *ssusb)
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{
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regulator_set_enable(ssusb->vbus_supply, false);
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ssusb_host_disable(ssusb->u3h);
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}
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