mirror of
https://github.com/brain-hackers/u-boot-brain
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e09b88cd08
This patch adds support for the MediaTek USB3 DRD controller, its host side is based on xHCI, this driver supports device mode and host mode. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Acked-by: Bin Meng <bmeng.cn@gmail.com>
425 lines
11 KiB
C
425 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* mtu3.h - MediaTek USB3 DRD header
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*
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* Copyright (C) 2016 MediaTek Inc.
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*
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* Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
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*/
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#ifndef __MTU3_H__
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#define __MTU3_H__
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#include <asm/io.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/devres.h>
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#include <generic-phy.h>
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#include <linux/bug.h>
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#include <linux/delay.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/usb/otg.h>
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#include <power/regulator.h>
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#include <usb/xhci.h>
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struct mtu3;
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struct mtu3_ep;
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struct mtu3_request;
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struct mtu3_host;
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#include "mtu3_hw_regs.h"
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#include "mtu3_qmu.h"
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#define MU3D_EP_TXCR0(epnum) (U3D_TX1CSR0 + (((epnum) - 1) * 0x10))
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#define MU3D_EP_TXCR1(epnum) (U3D_TX1CSR1 + (((epnum) - 1) * 0x10))
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#define MU3D_EP_TXCR2(epnum) (U3D_TX1CSR2 + (((epnum) - 1) * 0x10))
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#define MU3D_EP_RXCR0(epnum) (U3D_RX1CSR0 + (((epnum) - 1) * 0x10))
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#define MU3D_EP_RXCR1(epnum) (U3D_RX1CSR1 + (((epnum) - 1) * 0x10))
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#define MU3D_EP_RXCR2(epnum) (U3D_RX1CSR2 + (((epnum) - 1) * 0x10))
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#define USB_QMU_RQCSR(epnum) (U3D_RXQCSR1 + (((epnum) - 1) * 0x10))
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#define USB_QMU_RQSAR(epnum) (U3D_RXQSAR1 + (((epnum) - 1) * 0x10))
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#define USB_QMU_RQCPR(epnum) (U3D_RXQCPR1 + (((epnum) - 1) * 0x10))
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#define USB_QMU_TQCSR(epnum) (U3D_TXQCSR1 + (((epnum) - 1) * 0x10))
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#define USB_QMU_TQSAR(epnum) (U3D_TXQSAR1 + (((epnum) - 1) * 0x10))
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#define USB_QMU_TQCPR(epnum) (U3D_TXQCPR1 + (((epnum) - 1) * 0x10))
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#define SSUSB_U3_CTRL(p) (U3D_SSUSB_U3_CTRL_0P + ((p) * 0x08))
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#define SSUSB_U2_CTRL(p) (U3D_SSUSB_U2_CTRL_0P + ((p) * 0x08))
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#define MTU3_DRIVER_NAME "mtu3-gadget"
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#define DMA_ADDR_INVALID (~(dma_addr_t)0)
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#define MTU3_EP_ENABLED BIT(0)
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#define MTU3_EP_STALL BIT(1)
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#define MTU3_EP_WEDGE BIT(2)
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#define MTU3_EP_BUSY BIT(3)
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/* should be set as 1 */
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#define MTU3_U2_IP_SLOT_DEFAULT 1
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#define MTU3_U3_IP_SLOT_DEFAULT (MTU3_U2_IP_SLOT_DEFAULT)
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/**
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* IP TRUNK version
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* from 0x1003 version, USB3 Gen2 is supported, two changes affect driver:
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* 1. MAXPKT and MULTI bits layout of TXCSR1 and RXCSR1 are adjusted,
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* but not backward compatible
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* 2. QMU extend buffer length supported
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*/
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#define MTU3_TRUNK_VERS_1003 0x1003
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/**
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* Normally the device works on HS or SS, to simplify fifo management,
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* devide fifo into some 2*maxp parts, use bitmap to manage it; And
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* 32 bits size of bitmap is large enough, that means it can manage
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* up to 32KB/64KB fifo size.
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* NOTE: MTU3_U2/3IP_EP_FIFO_UNIT should be power of two;
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* FIFO size is allocated according to @slot which is 1 by default
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*/
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#define USB_HS_MAXP 512
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#define USB_SS_MAXP 1024
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#define MTU3_U2IP_EP_FIFO_UNIT \
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((USB_HS_MAXP) * ((MTU3_U2_IP_SLOT_DEFAULT) + 1))
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#define MTU3_U3IP_EP_FIFO_UNIT \
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((USB_SS_MAXP) * ((MTU3_U3_IP_SLOT_DEFAULT) + 1))
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#define MTU3_FIFO_BIT_SIZE 32
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#define MTU3_U2_IP_EP0_FIFO_SIZE 64
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/**
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* Maximum size of ep0 response buffer for ch9 requests,
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* the SET_SEL request uses 6 so far, and GET_STATUS is 2
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*/
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#define EP0_RESPONSE_BUF 6
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/* device operated link and speed got from DEVICE_CONF register */
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enum mtu3_speed {
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MTU3_SPEED_INACTIVE = 0,
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MTU3_SPEED_FULL = 1,
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MTU3_SPEED_HIGH = 3,
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MTU3_SPEED_SUPER = 4,
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MTU3_SPEED_SUPER_PLUS = 5,
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};
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/**
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* @MU3D_EP0_STATE_SETUP: waits for SETUP or received a SETUP
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* without data stage.
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* @MU3D_EP0_STATE_TX: IN data stage
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* @MU3D_EP0_STATE_RX: OUT data stage
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* @MU3D_EP0_STATE_TX_END: the last IN data is transferred, and
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* waits for its completion interrupt
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* @MU3D_EP0_STATE_STALL: ep0 is in stall status, will be auto-cleared
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* after receives a SETUP.
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*/
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enum mtu3_g_ep0_state {
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MU3D_EP0_STATE_SETUP = 1,
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MU3D_EP0_STATE_TX,
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MU3D_EP0_STATE_RX,
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MU3D_EP0_STATE_TX_END,
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MU3D_EP0_STATE_STALL,
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};
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/**
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* MTU3_DR_FORCE_NONE: automatically switch host and peripheral mode
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* by IDPIN signal.
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* MTU3_DR_FORCE_HOST: force to enter host mode and override OTG
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* IDPIN signal.
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* MTU3_DR_FORCE_DEVICE: force to enter peripheral mode.
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*/
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enum mtu3_dr_force_mode {
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MTU3_DR_FORCE_NONE = 0,
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MTU3_DR_FORCE_HOST,
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MTU3_DR_FORCE_DEVICE,
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};
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/**
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* @mac_base: register base address of MAC, include xHCI and device
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* @ippc_base: register base address of IP Power and Clock interface (IPPC)
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* @vusb33_supply: usb3.3V shared by device/host IP
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* @vbus_supply: vbus 5v of OTG port
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* @clks: optional clocks, include "sys_ck", "ref_ck", "mcu_ck",
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* "dma_ck" and "xhci_ck"
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* @phys: phys used
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* @dr_mode: works in which mode:
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* host only, device only or dual-role mode
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*/
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struct ssusb_mtk {
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struct udevice *dev;
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struct mtu3 *u3d;
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struct mtu3_host *u3h;
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void __iomem *mac_base;
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void __iomem *ippc_base;
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/* common power & clock */
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struct udevice *vusb33_supply;
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struct udevice *vbus_supply;
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struct clk_bulk clks;
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struct phy_bulk phys;
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/* otg */
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enum usb_dr_mode dr_mode;
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};
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/**
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* @ctrl: xHCI controller, needs to come first in this struct!
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* @hcd: xHCI's register base address
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* @u2_ports: number of usb2 host ports
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* @u3_ports: number of usb3 host ports
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* @u3p_dis_msk: mask of disabling usb3 ports, for example, bit0==1 to
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* disable u3port0, bit1==1 to disable u3port1,... etc
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*/
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struct mtu3_host {
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struct xhci_ctrl ctrl;
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struct xhci_hccr *hcd;
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void __iomem *ippc_base;
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struct ssusb_mtk *ssusb;
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struct udevice *dev;
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u32 u2_ports;
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u32 u3_ports;
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u32 u3p_dis_msk;
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};
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/**
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* @base: the base address of fifo
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* @limit: the bitmap size in bits
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* @bitmap: fifo bitmap in unit of @MTU3_EP_FIFO_UNIT
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*/
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struct mtu3_fifo_info {
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u32 base;
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u32 limit;
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DECLARE_BITMAP(bitmap, MTU3_FIFO_BIT_SIZE);
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};
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/**
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* General Purpose Descriptor (GPD):
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* The format of TX GPD is a little different from RX one.
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* And the size of GPD is 16 bytes.
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*
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* @flag:
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* bit0: Hardware Own (HWO)
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* bit1: Buffer Descriptor Present (BDP), always 0, BD is not supported
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* bit2: Bypass (BPS), 1: HW skips this GPD if HWO = 1
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* bit7: Interrupt On Completion (IOC)
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* @chksum: This is used to validate the contents of this GPD;
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* If TXQ_CS_EN / RXQ_CS_EN bit is set, an interrupt is issued
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* when checksum validation fails;
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* Checksum value is calculated over the 16 bytes of the GPD by default;
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* @data_buf_len (RX ONLY): This value indicates the length of
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* the assigned data buffer
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* @next_gpd: Physical address of the next GPD
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* @buffer: Physical address of the data buffer
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* @buf_len:
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* (TX): This value indicates the length of the assigned data buffer
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* (RX): The total length of data received
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* @ext_len: reserved
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* @ext_flag:
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* bit5 (TX ONLY): Zero Length Packet (ZLP),
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*/
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struct qmu_gpd {
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__u8 flag;
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__u8 chksum;
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__le16 data_buf_len;
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__le32 next_gpd;
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__le32 buffer;
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__le16 buf_len;
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__u8 ext_len;
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__u8 ext_flag;
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} __packed;
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/**
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* dma: physical base address of GPD segment
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* start: virtual base address of GPD segment
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* end: the last GPD element
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* enqueue: the first empty GPD to use
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* dequeue: the first completed GPD serviced by ISR
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* NOTE: the size of GPD ring should be >= 2
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*/
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struct mtu3_gpd_ring {
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dma_addr_t dma;
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struct qmu_gpd *start;
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struct qmu_gpd *end;
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struct qmu_gpd *enqueue;
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struct qmu_gpd *dequeue;
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};
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/**
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* @fifo_size: it is (@slot + 1) * @fifo_seg_size
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* @fifo_seg_size: it is roundup_pow_of_two(@maxp)
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*/
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struct mtu3_ep {
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struct usb_ep ep;
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char name[12];
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struct mtu3 *mtu;
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u8 epnum;
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u8 type;
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u8 is_in;
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u16 maxp;
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int slot;
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u32 fifo_size;
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u32 fifo_addr;
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u32 fifo_seg_size;
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struct mtu3_fifo_info *fifo;
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struct list_head req_list;
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struct mtu3_gpd_ring gpd_ring;
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const struct usb_ss_ep_comp_descriptor *comp_desc;
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const struct usb_endpoint_descriptor *desc;
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int flags;
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};
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struct mtu3_request {
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struct usb_request request;
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struct list_head list;
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struct mtu3_ep *mep;
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struct mtu3 *mtu;
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struct qmu_gpd *gpd;
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int epnum;
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};
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static inline struct ssusb_mtk *dev_to_ssusb(struct udevice *dev)
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{
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return dev_get_priv(dev);
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}
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/**
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* struct mtu3 - device driver instance data.
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* @slot: MTU3_U2_IP_SLOT_DEFAULT for U2 IP only,
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* MTU3_U3_IP_SLOT_DEFAULT for U3 IP
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* @may_wakeup: means device's remote wakeup is enabled
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* @is_self_powered: is reported in device status and the config descriptor
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* @delayed_status: true when function drivers ask for delayed status
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* @gen2cp: compatible with USB3 Gen2 IP
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* @ep0_req: dummy request used while handling standard USB requests
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* for GET_STATUS and SET_SEL
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* @setup_buf: ep0 response buffer for GET_STATUS and SET_SEL requests
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*/
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struct mtu3 {
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spinlock_t lock;
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struct ssusb_mtk *ssusb;
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struct udevice *dev;
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void __iomem *mac_base;
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void __iomem *ippc_base;
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int irq;
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struct mtu3_fifo_info tx_fifo;
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struct mtu3_fifo_info rx_fifo;
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struct mtu3_ep *ep_array;
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struct mtu3_ep *in_eps;
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struct mtu3_ep *out_eps;
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struct mtu3_ep *ep0;
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int num_eps;
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int slot;
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int active_ep;
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enum mtu3_g_ep0_state ep0_state;
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struct usb_gadget g; /* the gadget */
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struct usb_gadget_driver *gadget_driver;
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struct mtu3_request ep0_req;
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u8 setup_buf[EP0_RESPONSE_BUF];
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enum usb_device_speed max_speed;
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enum usb_device_speed speed;
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unsigned is_active:1;
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unsigned may_wakeup:1;
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unsigned is_self_powered:1;
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unsigned test_mode:1;
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unsigned softconnect:1;
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unsigned u1_enable:1;
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unsigned u2_enable:1;
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unsigned is_u3_ip:1;
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unsigned delayed_status:1;
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unsigned gen2cp:1;
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unsigned force_vbus:1;
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u8 address;
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u8 test_mode_nr;
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u32 hw_version;
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};
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static inline struct mtu3 *gadget_to_mtu3(struct usb_gadget *g)
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{
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return container_of(g, struct mtu3, g);
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}
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static inline int is_first_entry(const struct list_head *list,
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const struct list_head *head)
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{
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return list_is_last(head, list);
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}
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static inline struct mtu3_request *to_mtu3_request(struct usb_request *req)
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{
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return req ? container_of(req, struct mtu3_request, request) : NULL;
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}
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static inline struct mtu3_ep *to_mtu3_ep(struct usb_ep *ep)
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{
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return ep ? container_of(ep, struct mtu3_ep, ep) : NULL;
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}
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static inline struct mtu3_request *next_request(struct mtu3_ep *mep)
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{
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if (list_empty(&mep->req_list))
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return NULL;
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return list_first_entry(&mep->req_list, struct mtu3_request, list);
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}
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static inline void mtu3_writel(void __iomem *base, u32 offset, u32 data)
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{
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writel(data, base + offset);
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}
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static inline u32 mtu3_readl(void __iomem *base, u32 offset)
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{
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return readl(base + offset);
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}
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static inline void mtu3_setbits(void __iomem *base, u32 offset, u32 bits)
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{
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void __iomem *addr = base + offset;
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u32 tmp = readl(addr);
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writel((tmp | (bits)), addr);
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}
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static inline void mtu3_clrbits(void __iomem *base, u32 offset, u32 bits)
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{
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void __iomem *addr = base + offset;
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u32 tmp = readl(addr);
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writel((tmp & ~(bits)), addr);
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}
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int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks);
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struct usb_request *mtu3_alloc_request(struct usb_ep *ep, gfp_t gfp_flags);
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void mtu3_free_request(struct usb_ep *ep, struct usb_request *req);
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void mtu3_req_complete(struct mtu3_ep *mep,
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struct usb_request *req, int status);
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int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
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int interval, int burst, int mult);
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void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep);
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void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set);
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void mtu3_ep0_setup(struct mtu3 *mtu);
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void mtu3_start(struct mtu3 *mtu);
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void mtu3_stop(struct mtu3 *mtu);
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void mtu3_dev_on_off(struct mtu3 *mtu, int is_on);
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void mtu3_set_speed(struct mtu3 *mtu, enum usb_device_speed speed);
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int mtu3_gadget_setup(struct mtu3 *mtu);
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void mtu3_gadget_cleanup(struct mtu3 *mtu);
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void mtu3_gadget_reset(struct mtu3 *mtu);
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void mtu3_gadget_suspend(struct mtu3 *mtu);
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void mtu3_gadget_resume(struct mtu3 *mtu);
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void mtu3_gadget_disconnect(struct mtu3 *mtu);
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irqreturn_t mtu3_ep0_isr(struct mtu3 *mtu);
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extern const struct usb_ep_ops mtu3_ep0_ops;
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#endif
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