108 lines
2.7 KiB
C
108 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* 64-bit Periodic Interval Timer driver
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*
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* Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
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*
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <timer.h>
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#include <asm/io.h>
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#define MCHP_PIT64B_CR 0x00 /* Control Register */
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#define MCHP_PIT64B_CR_START BIT(0)
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#define MCHP_PIT64B_CR_SWRST BIT(8)
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#define MCHP_PIT64B_MR 0x04 /* Mode Register */
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#define MCHP_PIT64B_MR_CONT BIT(0)
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#define MCHP_PIT64B_LSB_PR 0x08 /* LSB Period Register */
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#define MCHP_PIT64B_MSB_PR 0x0C /* MSB Period Register */
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#define MCHP_PIT64B_TLSBR 0x20 /* Timer LSB Register */
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#define MCHP_PIT64B_TMSBR 0x24 /* Timer MSB Register */
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struct mchp_pit64b_priv {
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void __iomem *base;
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};
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static u64 mchp_pit64b_get_count(struct udevice *dev)
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{
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struct mchp_pit64b_priv *priv = dev_get_priv(dev);
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u32 lsb = readl(priv->base + MCHP_PIT64B_TLSBR);
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u32 msb = readl(priv->base + MCHP_PIT64B_TMSBR);
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return ((u64)msb << 32) | lsb;
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}
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static int mchp_pit64b_probe(struct udevice *dev)
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{
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struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct mchp_pit64b_priv *priv = dev_get_priv(dev);
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struct clk clk;
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ulong rate;
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int ret;
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priv->base = dev_read_addr_ptr(dev);
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if (IS_ERR(priv->base))
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return PTR_ERR(priv->base);
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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rate = clk_get_rate(&clk);
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if (!rate) {
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clk_disable(&clk);
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return -ENOTSUPP;
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}
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/* Reset the timer in case it was used by previous bootloaders. */
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writel(MCHP_PIT64B_CR_SWRST, priv->base + MCHP_PIT64B_CR);
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/*
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* Use highest prescaller (for a peripheral clock running at 200MHz
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* this will lead to the timer running at 12.5MHz) and continuous mode.
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*/
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writel((15 << 8) | MCHP_PIT64B_MR_CONT, priv->base + MCHP_PIT64B_MR);
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uc_priv->clock_rate = rate / 16;
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/*
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* Simulate free running counter by setting max values to period
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* registers.
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*/
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writel(~0UL, priv->base + MCHP_PIT64B_MSB_PR);
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writel(~0UL, priv->base + MCHP_PIT64B_LSB_PR);
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/* Start the timer. */
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writel(MCHP_PIT64B_CR_START, priv->base + MCHP_PIT64B_CR);
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return 0;
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}
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static const struct timer_ops mchp_pit64b_ops = {
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.get_count = mchp_pit64b_get_count,
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};
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static const struct udevice_id mchp_pit64b_ids[] = {
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{ .compatible = "microchip,sam9x60-pit64b", },
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{ .compatible = "microchip,sama7g5-pit64b", },
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{ }
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};
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U_BOOT_DRIVER(mchp_pit64b) = {
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.name = "mchp-pit64b",
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.id = UCLASS_TIMER,
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.of_match = mchp_pit64b_ids,
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.priv_auto = sizeof(struct mchp_pit64b_priv),
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.probe = mchp_pit64b_probe,
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.ops = &mchp_pit64b_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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