245 lines
5.9 KiB
C
245 lines
5.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*
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* This file is derived from the flashrom project.
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*/
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#ifndef _ICH_H_
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#define _ICH_H_
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#include <linux/bitops.h>
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struct ich7_spi_regs {
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uint16_t spis;
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uint16_t spic;
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uint32_t spia;
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uint64_t spid[8];
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uint64_t _pad;
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uint32_t bbar;
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uint16_t preop;
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uint16_t optype;
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uint8_t opmenu[8];
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} __packed;
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struct ich9_spi_regs {
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uint32_t bfpr; /* 0x00 */
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uint16_t hsfs;
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uint16_t hsfc;
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uint32_t faddr;
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uint32_t _reserved0;
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uint32_t fdata[16]; /* 0x10 */
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uint32_t frap; /* 0x50 */
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uint32_t freg[5];
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uint32_t _reserved1[3];
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uint32_t pr[5]; /* 0x74 */
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uint32_t _reserved2[2];
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uint8_t ssfs; /* 0x90 */
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uint8_t ssfc[3];
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uint16_t preop; /* 0x94 */
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uint16_t optype;
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uint8_t opmenu[8]; /* 0x98 */
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uint32_t bbar;
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uint8_t _reserved3[12];
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uint32_t fdoc; /* 0xb0 */
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uint32_t fdod;
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uint8_t _reserved4[8];
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uint32_t afc; /* 0xc0 */
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uint32_t lvscc;
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uint32_t uvscc;
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uint8_t _reserved5[4];
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uint32_t fpb; /* 0xd0 */
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uint8_t _reserved6[28];
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uint32_t srdl; /* 0xf0 */
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uint32_t srdc;
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uint32_t scs;
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uint32_t bcr;
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} __packed;
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enum {
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SPIS_SCIP = 0x0001,
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SPIS_GRANT = 0x0002,
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SPIS_CDS = 0x0004,
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SPIS_FCERR = 0x0008,
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SSFS_AEL = 0x0010,
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SPIS_LOCK = 0x8000,
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SPIS_RESERVED_MASK = 0x7ff0,
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SSFS_RESERVED_MASK = 0x7fe2
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};
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enum {
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SPIC_SCGO = 0x000002,
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SPIC_ACS = 0x000004,
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SPIC_SPOP = 0x000008,
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SPIC_DBC = 0x003f00,
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SPIC_DS = 0x004000,
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SPIC_SME = 0x008000,
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SSFC_SCF_MASK = 0x070000,
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SSFC_RESERVED = 0xf80000,
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/* Mask for speed byte, biuts 23:16 of SSFC */
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SSFC_SCF_33MHZ = 0x01,
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};
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enum {
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HSFS_FDONE = 0x0001,
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HSFS_FCERR = 0x0002,
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HSFS_AEL = 0x0004,
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HSFS_BERASE_MASK = 0x0018,
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HSFS_BERASE_SHIFT = 3,
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HSFS_SCIP = 0x0020,
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HSFS_FDOPSS = 0x2000,
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HSFS_FDV = 0x4000,
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HSFS_FLOCKDN = 0x8000
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};
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enum {
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HSFC_FGO = 0x0001,
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HSFC_FCYCLE_MASK = 0x0006,
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HSFC_FCYCLE_SHIFT = 1,
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HSFC_FDBC_MASK = 0x3f00,
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HSFC_FDBC_SHIFT = 8,
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HSFC_FSMIE = 0x8000
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};
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struct spi_trans {
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uint8_t cmd;
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const uint8_t *out;
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uint32_t bytesout;
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uint8_t *in;
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uint32_t bytesin;
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uint8_t type;
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uint8_t opcode;
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uint32_t offset;
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};
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#define SPI_OPCODE_WRSR 0x01
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#define SPI_OPCODE_PAGE_PROGRAM 0x02
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#define SPI_OPCODE_READ 0x03
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#define SPI_OPCODE_WRDIS 0x04
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#define SPI_OPCODE_RDSR 0x05
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#define SPI_OPCODE_WREN 0x06
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#define SPI_OPCODE_FAST_READ 0x0b
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#define SPI_OPCODE_ERASE_SECT 0x20
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#define SPI_OPCODE_READ_ID 0x9f
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#define SPI_OPCODE_ERASE_BLOCK 0xd8
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#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
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#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
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#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
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#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
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#define SPI_OPMENU_0 SPI_OPCODE_WRSR
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#define SPI_OPTYPE_0 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
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#define SPI_OPMENU_1 SPI_OPCODE_PAGE_PROGRAM
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#define SPI_OPTYPE_1 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
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#define SPI_OPMENU_2 SPI_OPCODE_READ
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#define SPI_OPTYPE_2 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
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#define SPI_OPMENU_3 SPI_OPCODE_RDSR
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#define SPI_OPTYPE_3 SPI_OPCODE_TYPE_READ_NO_ADDRESS
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#define SPI_OPMENU_4 SPI_OPCODE_ERASE_SECT
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#define SPI_OPTYPE_4 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
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#define SPI_OPMENU_5 SPI_OPCODE_READ_ID
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#define SPI_OPTYPE_5 SPI_OPCODE_TYPE_READ_NO_ADDRESS
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#define SPI_OPMENU_6 SPI_OPCODE_ERASE_BLOCK
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#define SPI_OPTYPE_6 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
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#define SPI_OPMENU_7 SPI_OPCODE_FAST_READ
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#define SPI_OPTYPE_7 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
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#define SPI_OPPREFIX ((SPI_OPCODE_WREN << 8) | SPI_OPCODE_WREN)
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#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
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(SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
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(SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
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(SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0))
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#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
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(SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0))
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#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
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(SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0))
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#define ICH_BOUNDARY 0x1000
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#define HSFSTS_FDBC_SHIFT 24
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#define HSFSTS_FDBC_MASK (0x3f << HSFSTS_FDBC_SHIFT)
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#define HSFSTS_WET BIT(21)
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#define HSFSTS_FCYCLE_SHIFT 17
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#define HSFSTS_FCYCLE_MASK (0xf << HSFSTS_FCYCLE_SHIFT)
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/* Supported flash cycle types */
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enum hsfsts_cycle_t {
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HSFSTS_CYCLE_READ = 0,
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HSFSTS_CYCLE_WRITE = 2,
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HSFSTS_CYCLE_4K_ERASE,
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HSFSTS_CYCLE_64K_ERASE,
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HSFSTS_CYCLE_RDSFDP,
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HSFSTS_CYCLE_RDID,
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HSFSTS_CYCLE_WR_STATUS,
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HSFSTS_CYCLE_RD_STATUS,
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};
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#define HSFSTS_FGO BIT(16)
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#define HSFSTS_FLOCKDN BIT(15)
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#define HSFSTS_FDV BIT(14)
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#define HSFSTS_FDOPSS BIT(13)
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#define HSFSTS_WRSDIS BIT(11)
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#define HSFSTS_SAF_CE BIT(8)
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#define HSFSTS_SAF_ACTIVE BIT(7)
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#define HSFSTS_SAF_LE BIT(6)
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#define HSFSTS_SCIP BIT(5)
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#define HSFSTS_SAF_DLE BIT(4)
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#define HSFSTS_SAF_ERROR BIT(3)
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#define HSFSTS_AEL BIT(2)
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#define HSFSTS_FCERR BIT(1)
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#define HSFSTS_FDONE BIT(0)
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#define HSFSTS_W1C_BITS 0xff
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/* Maximum bytes of data that can fit in FDATAn (0x10) registers */
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#define SPIBAR_FDATA_FIFO_SIZE 0x40
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#define SPIBAR_HWSEQ_XFER_TIMEOUT_MS 5000
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enum ich_version {
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ICHV_7,
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ICHV_9,
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ICHV_APL,
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};
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struct ich_spi_priv {
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int opmenu;
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int menubytes;
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void *base; /* Base of register set */
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int preop;
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int optype;
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int addr;
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int data;
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unsigned databytes;
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int status;
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int control;
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int bbar;
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int bcr;
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uint32_t *pr; /* only for ich9 */
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int speed; /* pointer to speed control */
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ulong max_speed; /* Maximum bus speed in MHz */
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ulong cur_speed; /* Current bus speed */
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struct spi_trans trans; /* current transaction in progress */
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struct udevice *pch; /* PCH, used to control SPI access */
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};
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struct ich_spi_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_intel_fast_spi dtplat;
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#endif
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enum ich_version ich_version; /* Controller version, 7 or 9 */
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bool lockdown; /* lock down controller settings? */
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ulong mmio_base; /* Base of MMIO registers */
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pci_dev_t bdf; /* PCI address used by of-platdata */
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bool hwseq; /* Use hardware sequencing (not s/w) */
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};
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#endif /* _ICH_H_ */
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