mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 07:16:04 +09:00
39edfaa758
Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3. For TPL_BUILD, the driver implement full dram init and without DM support due to the limit of internal SRAM size. For SPL and U-Boot proper, it's a simple driver with dm for get dram_info like other SoCs. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
75 lines
1.8 KiB
PHP
75 lines
1.8 KiB
PHP
{
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{
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{
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.rank = 0x1,
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.col = 0xC,
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.bk = 0x3,
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.bw = 0x1,
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.dbw = 0x0,
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.row_3_4 = 0x0,
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.cs0_row = 0x10,
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.cs1_row = 0x10,
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.cs0_high16bit_row = 0x10,
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.cs1_high16bit_row = 0x10,
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.ddrconfig = 0,
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},
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{
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{0x290a060a},
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{0x08020303},
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{0x00000002},
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{0x00001111},
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{0x0000000c},
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{0x0000021a},
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0x000000ff
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}
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},
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{
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.ddr_freq = 333,
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.dramtype = LPDDR3,
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.num_channels = 1,
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.stride = 0,
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.odt = 0,
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},
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{
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{
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{0x00000000, 0x43041008}, /* MSTR */
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{0x00000064, 0x00140023}, /* RFSHTMG */
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{0x000000d0, 0x00220002}, /* INIT0 */
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{0x000000d4, 0x00010000}, /* INIT1 */
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{0x000000d8, 0x00000703}, /* INIT2 */
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{0x000000dc, 0x00830004}, /* INIT3 */
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{0x000000e0, 0x00010000}, /* INIT4 */
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{0x000000e4, 0x00070003}, /* INIT5 */
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{0x000000f4, 0x000f012f}, /* RANKCTL */
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{0x00000100, 0x06090b07}, /* DRAMTMG0 */
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{0x00000104, 0x0002020b}, /* DRAMTMG1 */
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{0x00000108, 0x02030506}, /* DRAMTMG2 */
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{0x0000010c, 0x00505000}, /* DRAMTMG3 */
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{0x00000110, 0x03020204}, /* DRAMTMG4 */
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{0x00000114, 0x01010303}, /* DRAMTMG5 */
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{0x00000118, 0x02020003}, /* DRAMTMG6 */
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{0x00000120, 0x00000303}, /* DRAMTMG8 */
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{0x00000138, 0x00000025}, /* DRAMTMG14 */
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{0x00000180, 0x003c000f}, /* ZQCTL0 */
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{0x00000184, 0x00900000}, /* ZQCTL1 */
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{0x00000190, 0x07020000}, /* DFITMG0 */
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{0x00000198, 0x07000101}, /* DFILPCFG0 */
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{0x000001a0, 0xc0400003}, /* DFIUPD0 */
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{0x00000240, 0x0900090c}, /* ODTCFG */
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{0x00000244, 0x00000101}, /* ODTMAP */
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{0x00000250, 0x00001f00}, /* SCHED */
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{0x00000490, 0x00000001}, /* PCTRL_0 */
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{0xffffffff, 0xffffffff}
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}
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},
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{
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{
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{0x00000004, 0x0000000b}, /* PHYREG01 */
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{0x00000028, 0x00000006}, /* PHYREG0A */
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{0x0000002c, 0x00000000}, /* PHYREG0B */
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{0x00000030, 0x00000003}, /* PHYREG0C */
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{0xffffffff, 0xffffffff}
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}
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}
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},
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