446 lines
11 KiB
C
446 lines
11 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_SANITY_H
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#define LPDDR4_SANITY_H
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#include <errno.h>
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#include <linux/types.h>
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#include "lpddr4_if.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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static inline u32 lpddr4_configsf(const lpddr4_config *obj);
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static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj);
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static inline u32 lpddr4_sanityfunction1(const lpddr4_config *config, const u16 *configsize);
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static inline u32 lpddr4_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_config *cfg);
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static inline u32 lpddr4_sanityfunction3(const lpddr4_privatedata *pd);
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static inline u32 lpddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue);
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static inline u32 lpddr4_sanityfunction5(const lpddr4_privatedata *pd, const lpddr4_regblock cpp);
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static inline u32 lpddr4_sanityfunction6(const lpddr4_privatedata *pd, const u64 *mmrvalue, const u8 *mmrstatus);
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static inline u32 lpddr4_sanityfunction7(const lpddr4_privatedata *pd, const u8 *mrwstatus);
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static inline u32 lpddr4_sanityfunction14(const lpddr4_privatedata *pd, const u64 *mask);
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static inline u32 lpddr4_sanityfunction15(const lpddr4_privatedata *pd, const u64 *mask);
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static inline u32 lpddr4_sanityfunction16(const lpddr4_privatedata *pd, const u32 *mask);
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static inline u32 lpddr4_sanityfunction18(const lpddr4_privatedata *pd, const lpddr4_debuginfo *debuginfo);
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static inline u32 lpddr4_sanityfunction19(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
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static inline u32 lpddr4_sanityfunction21(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
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static inline u32 lpddr4_sanityfunction22(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
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static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
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static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
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static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off);
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static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
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static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
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static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
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#define lpddr4_probesf lpddr4_sanityfunction1
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#define lpddr4_initsf lpddr4_sanityfunction2
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#define lpddr4_startsf lpddr4_sanityfunction3
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#define lpddr4_readregsf lpddr4_sanityfunction4
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#define lpddr4_writeregsf lpddr4_sanityfunction5
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#define lpddr4_getmmrregistersf lpddr4_sanityfunction6
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#define lpddr4_setmmrregistersf lpddr4_sanityfunction7
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#define lpddr4_writectlconfigsf lpddr4_sanityfunction3
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#define lpddr4_writephyconfigsf lpddr4_sanityfunction3
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#define lpddr4_writephyindepconfigsf lpddr4_sanityfunction3
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#define lpddr4_readctlconfigsf lpddr4_sanityfunction3
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#define lpddr4_readphyconfigsf lpddr4_sanityfunction3
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#define lpddr4_readphyindepconfigsf lpddr4_sanityfunction3
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#define lpddr4_getctlinterruptmasksf lpddr4_sanityfunction14
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#define lpddr4_setctlinterruptmasksf lpddr4_sanityfunction15
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#define lpddr4_getphyindepinterruptmsf lpddr4_sanityfunction16
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#define lpddr4_setphyindepinterruptmsf lpddr4_sanityfunction16
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#define lpddr4_getdebuginitinfosf lpddr4_sanityfunction18
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#define lpddr4_getlpiwakeuptimesf lpddr4_sanityfunction19
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#define lpddr4_setlpiwakeuptimesf lpddr4_sanityfunction19
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#define lpddr4_geteccenablesf lpddr4_sanityfunction21
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#define lpddr4_seteccenablesf lpddr4_sanityfunction22
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#define lpddr4_getreducmodesf lpddr4_sanityfunction23
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#define lpddr4_setreducmodesf lpddr4_sanityfunction24
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#define lpddr4_getdbireadmodesf lpddr4_sanityfunction25
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#define lpddr4_getdbiwritemodesf lpddr4_sanityfunction25
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#define lpddr4_setdbimodesf lpddr4_sanityfunction27
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#define lpddr4_getrefreshratesf lpddr4_sanityfunction28
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#define lpddr4_setrefreshratesf lpddr4_sanityfunction29
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#define lpddr4_refreshperchipselectsf lpddr4_sanityfunction3
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static inline u32 lpddr4_configsf(const lpddr4_config *obj)
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{
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u32 ret = 0;
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if (obj == NULL)
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ret = EINVAL;
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return ret;
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}
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static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj)
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{
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u32 ret = 0;
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if (obj == NULL)
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ret = EINVAL;
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return ret;
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}
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static inline u32 lpddr4_sanityfunction1(const lpddr4_config *config, const u16 *configsize)
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{
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u32 ret = 0;
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if (configsize == NULL) {
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ret = EINVAL;
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} else if (lpddr4_configsf(config) == EINVAL) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_config *cfg)
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{
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u32 ret = 0;
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if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else if (lpddr4_configsf(cfg) == EINVAL) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction3(const lpddr4_privatedata *pd)
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{
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u32 ret = 0;
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if (lpddr4_privatedatasf(pd) == EINVAL)
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ret = EINVAL;
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return ret;
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}
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static inline u32 lpddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue)
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{
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u32 ret = 0;
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if (regvalue == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else if (
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(cpp != LPDDR4_CTL_REGS) &&
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(cpp != LPDDR4_PHY_REGS) &&
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(cpp != LPDDR4_PHY_INDEP_REGS)
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) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction5(const lpddr4_privatedata *pd, const lpddr4_regblock cpp)
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{
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u32 ret = 0;
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if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else if (
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(cpp != LPDDR4_CTL_REGS) &&
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(cpp != LPDDR4_PHY_REGS) &&
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(cpp != LPDDR4_PHY_INDEP_REGS)
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) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction6(const lpddr4_privatedata *pd, const u64 *mmrvalue, const u8 *mmrstatus)
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{
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u32 ret = 0;
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if (mmrvalue == NULL) {
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ret = EINVAL;
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} else if (mmrstatus == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction7(const lpddr4_privatedata *pd, const u8 *mrwstatus)
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{
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u32 ret = 0;
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if (mrwstatus == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction14(const lpddr4_privatedata *pd, const u64 *mask)
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{
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u32 ret = 0;
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if (mask == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction15(const lpddr4_privatedata *pd, const u64 *mask)
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{
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u32 ret = 0;
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if (mask == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction16(const lpddr4_privatedata *pd, const u32 *mask)
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{
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u32 ret = 0;
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if (mask == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction18(const lpddr4_privatedata *pd, const lpddr4_debuginfo *debuginfo)
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{
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u32 ret = 0;
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if (debuginfo == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction19(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
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{
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u32 ret = 0;
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if (lpiwakeupparam == NULL) {
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ret = EINVAL;
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} else if (fspnum == NULL) {
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ret = EINVAL;
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} else if (cycles == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else if (
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(*lpiwakeupparam != LPDDR4_LPI_PD_WAKEUP_FN) &&
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(*lpiwakeupparam != LPDDR4_LPI_SR_SHORT_WAKEUP_FN) &&
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(*lpiwakeupparam != LPDDR4_LPI_SR_LONG_WAKEUP_FN) &&
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(*lpiwakeupparam != LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) &&
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(*lpiwakeupparam != LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) &&
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(*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) &&
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(*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN)
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) {
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ret = EINVAL;
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} else if (
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(*fspnum != LPDDR4_FSP_0) &&
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(*fspnum != LPDDR4_FSP_1) &&
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(*fspnum != LPDDR4_FSP_2)
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) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction21(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
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{
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u32 ret = 0;
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if (eccparam == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction22(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
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{
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u32 ret = 0;
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if (eccparam == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else if (
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(*eccparam != LPDDR4_ECC_DISABLED) &&
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(*eccparam != LPDDR4_ECC_ENABLED) &&
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(*eccparam != LPDDR4_ECC_ERR_DETECT) &&
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(*eccparam != LPDDR4_ECC_ERR_DETECT_CORRECT)
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) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
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{
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u32 ret = 0;
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if (mode == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
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{
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u32 ret = 0;
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if (mode == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else if (
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(*mode != LPDDR4_REDUC_ON) &&
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(*mode != LPDDR4_REDUC_OFF)
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) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off)
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{
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u32 ret = 0;
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if (on_off == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode)
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{
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u32 ret = 0;
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if (mode == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else if (
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(*mode != LPDDR4_DBI_RD_ON) &&
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(*mode != LPDDR4_DBI_RD_OFF) &&
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(*mode != LPDDR4_DBI_WR_ON) &&
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(*mode != LPDDR4_DBI_WR_OFF)
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) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
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{
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u32 ret = 0;
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if (fspnum == NULL) {
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ret = EINVAL;
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} else if (tref == NULL) {
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ret = EINVAL;
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} else if (tras_max == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else if (
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(*fspnum != LPDDR4_FSP_0) &&
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(*fspnum != LPDDR4_FSP_1) &&
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(*fspnum != LPDDR4_FSP_2)
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) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
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{
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u32 ret = 0;
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if (fspnum == NULL) {
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ret = EINVAL;
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} else if (tref == NULL) {
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ret = EINVAL;
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} else if (tras_max == NULL) {
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ret = EINVAL;
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} else if (lpddr4_privatedatasf(pd) == EINVAL) {
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ret = EINVAL;
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} else if (
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(*fspnum != LPDDR4_FSP_0) &&
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(*fspnum != LPDDR4_FSP_1) &&
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(*fspnum != LPDDR4_FSP_2)
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) {
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ret = EINVAL;
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} else {
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}
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return ret;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* LPDDR4_SANITY_H */
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