mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
a8c13c777e
Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
87 lines
3.5 KiB
C
87 lines
3.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef lpddr4_obj_if_h
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#define lpddr4_obj_if_h
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#include "lpddr4_if.h"
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typedef struct lpddr4_obj_s {
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u32 (*probe)(const lpddr4_config *config, u16 *configsize);
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u32 (*init)(lpddr4_privatedata *pd, const lpddr4_config *cfg);
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u32 (*start)(const lpddr4_privatedata *pd);
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u32 (*readreg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue);
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u32 (*writereg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
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u32 (*getmmrregister)(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus);
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u32 (*setmmrregister)(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus);
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u32 (*writectlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
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u32 (*writephyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
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u32 (*writephyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
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u32 (*readctlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
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u32 (*readphyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
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u32 (*readphyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
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u32 (*getctlinterruptmask)(const lpddr4_privatedata *pd, u64 *mask);
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u32 (*setctlinterruptmask)(const lpddr4_privatedata *pd, const u64 *mask);
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u32 (*checkctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
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u32 (*ackctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr);
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u32 (*getphyindepinterruptmask)(const lpddr4_privatedata *pd, u32 *mask);
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u32 (*setphyindepinterruptmask)(const lpddr4_privatedata *pd, const u32 *mask);
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u32 (*checkphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus);
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u32 (*ackphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr);
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u32 (*getdebuginitinfo)(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo);
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u32 (*getlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
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u32 (*setlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
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u32 (*geteccenable)(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam);
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u32 (*seteccenable)(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
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u32 (*getreducmode)(const lpddr4_privatedata *pd, lpddr4_reducmode *mode);
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u32 (*setreducmode)(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
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u32 (*getdbireadmode)(const lpddr4_privatedata *pd, bool *on_off);
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u32 (*getdbiwritemode)(const lpddr4_privatedata *pd, bool *on_off);
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u32 (*setdbimode)(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
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u32 (*getrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max);
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u32 (*setrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
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u32 (*refreshperchipselect)(const lpddr4_privatedata *pd, const u32 trefinterval);
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} lpddr4_obj;
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extern lpddr4_obj *lpddr4_getinstance(void);
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#endif /* lpddr4_obj_if_h */
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