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https://github.com/brain-hackers/u-boot-brain
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a8c13c777e
Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
24 lines
688 B
C
24 lines
688 B
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2021 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_RW_MASKS_H_
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#define LPDDR4_RW_MASKS_H_
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#include <stdint.h>
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extern u32 g_lpddr4_ddr_controller_rw_mask[459];
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extern u32 g_lpddr4_pi_rw_mask[300];
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extern u32 g_lpddr4_data_slice_0_rw_mask[140];
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extern u32 g_lpddr4_data_slice_1_rw_mask[140];
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extern u32 g_lpddr4_data_slice_2_rw_mask[140];
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extern u32 g_lpddr4_data_slice_3_rw_mask[140];
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extern u32 g_lpddr4_address_slice_0_rw_mask[52];
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extern u32 g_lpddr4_phy_core_rw_mask[143];
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#endif /* LPDDR4_RW_MASKS_H_ */
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