mirror of
https://github.com/brain-hackers/u-boot-brain
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caa4daa2ae
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
155 lines
3.2 KiB
C
155 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Google, Inc
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* Written by Simon Glass <sjg@chromium.org>
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*
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* Based on Rockchip's drivers/power/pmic/pmic_act8846.c:
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* Copyright (C) 2012 rockchips
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* zyw <zyw@rock-chips.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <power/act8846_pmic.h>
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#include <power/pmic.h>
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#include <power/regulator.h>
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static const u16 voltage_map[] = {
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600, 625, 650, 675, 700, 725, 750, 775,
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800, 825, 850, 875, 900, 925, 950, 975,
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1000, 1025, 1050, 1075, 1100, 1125, 1150, 1175,
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1200, 1250, 1300, 1350, 1400, 1450, 1500, 1550,
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1600, 1650, 1700, 1750, 1800, 1850, 1900, 1950,
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2000, 2050, 2100, 2150, 2200, 2250, 2300, 2350,
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2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100,
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3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900,
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};
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enum {
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REG_SYS0,
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REG_SYS1,
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REG1_VOL = 0x10,
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REG1_CTL = 0X11,
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REG2_VOL0 = 0x20,
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REG2_VOL1,
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REG2_CTL,
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REG3_VOL0 = 0x30,
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REG3_VOL1,
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REG3_CTL,
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REG4_VOL0 = 0x40,
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REG4_VOL1,
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REG4_CTL,
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REG5_VOL = 0x50,
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REG5_CTL,
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REG6_VOL = 0X58,
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REG6_CTL,
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REG7_VOL = 0x60,
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REG7_CTL,
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REG8_VOL = 0x68,
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REG8_CTL,
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REG9_VOL = 0x70,
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REG9_CTL,
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REG10_VOL = 0x80,
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REG10_CTL,
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REG11_VOL = 0x90,
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REG11_CTL,
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REG12_VOL = 0xa0,
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REG12_CTL,
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REG13 = 0xb1,
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};
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static const u8 addr_vol[] = {
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0, REG1_VOL, REG2_VOL0, REG3_VOL0, REG4_VOL0,
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REG5_VOL, REG6_VOL, REG7_VOL, REG8_VOL, REG9_VOL,
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REG10_VOL, REG11_VOL, REG12_VOL,
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};
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static const u8 addr_ctl[] = {
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0, REG1_CTL, REG2_CTL, REG3_CTL, REG4_CTL,
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REG5_CTL, REG6_CTL, REG7_CTL, REG8_CTL, REG9_CTL,
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REG10_CTL, REG11_CTL, REG12_CTL,
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};
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static int check_volt_table(const u16 *volt_table, int uvolt)
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{
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int i;
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for (i = VOL_MIN_IDX; i < VOL_MAX_IDX; i++) {
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if (uvolt <= (volt_table[i] * 1000))
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return i;
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}
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return -EINVAL;
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}
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static int reg_get_value(struct udevice *dev)
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{
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int reg = dev->driver_data;
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int ret;
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ret = pmic_reg_read(dev->parent, addr_vol[reg]);
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if (ret < 0)
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return ret;
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return voltage_map[ret & LDO_VOL_MASK] * 1000;
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}
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static int reg_set_value(struct udevice *dev, int uvolt)
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{
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int reg = dev->driver_data;
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int val;
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val = check_volt_table(voltage_map, uvolt);
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if (val < 0)
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return val;
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return pmic_clrsetbits(dev->parent, addr_vol[reg], LDO_VOL_MASK, val);
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}
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static int reg_set_enable(struct udevice *dev, bool enable)
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{
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int reg = dev->driver_data;
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return pmic_clrsetbits(dev->parent, addr_ctl[reg], LDO_EN_MASK,
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enable ? LDO_EN_MASK : 0);
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}
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static int reg_get_enable(struct udevice *dev)
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{
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int reg = dev->driver_data;
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int ret;
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ret = pmic_reg_read(dev->parent, addr_ctl[reg]);
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if (ret < 0)
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return ret;
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return ret & LDO_EN_MASK ? true : false;
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}
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static int act8846_reg_probe(struct udevice *dev)
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{
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struct dm_regulator_uclass_plat *uc_pdata;
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int reg = dev->driver_data;
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uc_pdata = dev_get_uclass_plat(dev);
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uc_pdata->type = reg <= 4 ? REGULATOR_TYPE_BUCK : REGULATOR_TYPE_LDO;
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uc_pdata->mode_count = 0;
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return 0;
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}
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static const struct dm_regulator_ops act8846_reg_ops = {
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.get_value = reg_get_value,
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.set_value = reg_set_value,
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.get_enable = reg_get_enable,
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.set_enable = reg_set_enable,
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};
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U_BOOT_DRIVER(act8846_buck) = {
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.name = "act8846_reg",
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.id = UCLASS_REGULATOR,
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.ops = &act8846_reg_ops,
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.probe = act8846_reg_probe,
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};
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