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https://github.com/brain-hackers/u-boot-brain
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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
325 lines
8.0 KiB
C
325 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <linux/bitops.h>
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#include "pinctrl-rockchip.h"
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static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
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{
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/* uart2dbga_rx */
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.bank_num = 4,
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.pin = 8,
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.func = 2,
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.route_offset = 0xe21c,
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.route_val = BIT(16 + 10) | BIT(16 + 11),
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}, {
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/* uart2dbgb_rx */
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.bank_num = 4,
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.pin = 16,
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.func = 2,
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.route_offset = 0xe21c,
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.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
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}, {
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/* uart2dbgc_rx */
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.bank_num = 4,
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.pin = 19,
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.func = 1,
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.route_offset = 0xe21c,
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.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
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}, {
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/* pcie_clkreqn */
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.bank_num = 2,
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.pin = 26,
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.func = 2,
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.route_offset = 0xe21c,
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.route_val = BIT(16 + 14),
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}, {
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/* pcie_clkreqnb */
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.bank_num = 4,
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.pin = 24,
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.func = 1,
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.route_offset = 0xe21c,
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.route_val = BIT(16 + 14) | BIT(14),
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},
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};
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static int rk3399_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, ret, mask, mux_type;
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u8 bit;
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u32 data, route_reg, route_val;
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regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
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? priv->regmap_pmu : priv->regmap_base;
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/* get basic quadrupel of mux registers and the correct reg inside */
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mux_type = bank->iomux[iomux_num].type;
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reg = bank->iomux[iomux_num].offset;
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reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
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if (bank->route_mask & BIT(pin)) {
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if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
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&route_val)) {
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ret = regmap_write(regmap, route_reg, route_val);
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if (ret)
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return ret;
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}
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}
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data = (mask << (bit + 16));
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data |= (mux & mask) << bit;
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3399_PULL_GRF_OFFSET 0xe040
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#define RK3399_PULL_PMU_OFFSET 0x40
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static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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/* The bank0:16 and bank1:32 pins are located in PMU */
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if (bank->bank_num == 0 || bank->bank_num == 1) {
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*regmap = priv->regmap_pmu;
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*reg = RK3399_PULL_PMU_OFFSET;
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*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
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} else {
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*regmap = priv->regmap_base;
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*reg = RK3399_PULL_GRF_OFFSET;
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/* correct the offset, as we're starting with the 3rd bank */
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*reg -= 0x20;
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*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
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}
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*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
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*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
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*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
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}
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static int rk3399_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct regmap *regmap;
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int reg, ret;
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u8 bit, type;
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u32 data;
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if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
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return -ENOTSUPP;
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rk3399_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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type = bank->pull_type[pin_num / 8];
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ret = rockchip_translate_pull_value(type, pull);
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if (ret < 0) {
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debug("unsupported pull setting %d\n", pull);
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return ret;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int drv_num = (pin_num / 8);
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/* The bank0:16 and bank1:32 pins are located in PMU */
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if (bank->bank_num == 0 || bank->bank_num == 1)
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*regmap = priv->regmap_pmu;
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else
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*regmap = priv->regmap_base;
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*reg = bank->drv[drv_num].offset;
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if (bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO ||
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bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)
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*bit = (pin_num % 8) * 3;
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else
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*bit = (pin_num % 8) * 2;
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}
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static int rk3399_set_drive(struct rockchip_pin_bank *bank,
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int pin_num, int strength)
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{
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struct regmap *regmap;
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int reg, ret;
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u32 data, rmask_bits, temp;
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u8 bit;
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int drv_type = bank->drv[pin_num / 8].drv_type;
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rk3399_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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ret = rockchip_translate_drive_value(drv_type, strength);
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if (ret < 0) {
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debug("unsupported driver strength %d\n", strength);
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return ret;
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}
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switch (drv_type) {
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case DRV_TYPE_IO_1V8_3V0_AUTO:
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case DRV_TYPE_IO_3V3_ONLY:
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rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
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switch (bit) {
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case 0 ... 12:
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/* regular case, nothing to do */
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break;
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case 15:
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/*
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* drive-strength offset is special, as it is spread
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* over 2 registers, the bit data[15] contains bit 0
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* of the value while temp[1:0] contains bits 2 and 1
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*/
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data = (ret & 0x1) << 15;
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temp = (ret >> 0x1) & 0x3;
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data |= BIT(31);
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ret = regmap_write(regmap, reg, data);
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if (ret)
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return ret;
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temp |= (0x3 << 16);
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reg += 0x4;
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ret = regmap_write(regmap, reg, temp);
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return ret;
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case 18 ... 21:
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/* setting fully enclosed in the second register */
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reg += 4;
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bit -= 16;
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break;
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default:
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debug("unsupported bit: %d for pinctrl drive type: %d\n",
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bit, drv_type);
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return -EINVAL;
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}
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break;
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case DRV_TYPE_IO_DEFAULT:
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case DRV_TYPE_IO_1V8_OR_3V0:
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case DRV_TYPE_IO_1V8_ONLY:
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rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
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break;
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default:
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debug("unsupported pinctrl drive type: %d\n",
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drv_type);
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return -EINVAL;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << rmask_bits) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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static struct rockchip_pin_bank rk3399_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_DEFAULT,
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DRV_TYPE_IO_DEFAULT,
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0x80,
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0x88,
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-1,
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-1,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_IO_DEFAULT,
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PULL_TYPE_IO_DEFAULT
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),
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PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_OR_3V0,
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0xa0,
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0xa8,
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0xb0,
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0xb8
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),
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PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_1V8_ONLY,
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PULL_TYPE_IO_DEFAULT,
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PULL_TYPE_IO_DEFAULT,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_IO_1V8_ONLY
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),
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PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
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DRV_TYPE_IO_3V3_ONLY,
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DRV_TYPE_IO_3V3_ONLY,
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DRV_TYPE_IO_1V8_OR_3V0
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),
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PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_3V0_AUTO,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_OR_3V0
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),
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};
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static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
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.pin_banks = rk3399_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3399_pin_banks),
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.grf_mux_offset = 0xe000,
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.pmu_mux_offset = 0x0,
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.grf_drv_offset = 0xe100,
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.pmu_drv_offset = 0x80,
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.iomux_routes = rk3399_mux_route_data,
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.niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
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.set_mux = rk3399_set_mux,
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.set_pull = rk3399_set_pull,
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.set_drive = rk3399_set_drive,
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};
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static const struct udevice_id rk3399_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rk3399-pinctrl",
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.data = (ulong)&rk3399_pin_ctrl
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},
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk3399) = {
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.name = "rockchip_rk3399_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3399_pinctrl_ids,
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.priv_auto = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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