mirror of
https://github.com/brain-hackers/u-boot-brain
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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
467 lines
9.8 KiB
C
467 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <linux/bitops.h>
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#include "pinctrl-rockchip.h"
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static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = {
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{
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.num = 1,
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.pin = 14,
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.reg = 0x28,
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.bit = 12,
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.mask = 0xf
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}, {
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.num = 1,
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.pin = 15,
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.reg = 0x2c,
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.bit = 0,
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.mask = 0x3
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}, {
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.num = 1,
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.pin = 18,
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.reg = 0x30,
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.bit = 4,
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.mask = 0xf
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}, {
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.num = 1,
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.pin = 19,
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.reg = 0x30,
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.bit = 8,
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.mask = 0xf
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}, {
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.num = 1,
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.pin = 20,
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.reg = 0x30,
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.bit = 12,
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.mask = 0xf
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}, {
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.num = 1,
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.pin = 21,
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.reg = 0x34,
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.bit = 0,
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.mask = 0xf
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}, {
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.num = 1,
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.pin = 22,
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.reg = 0x34,
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.bit = 4,
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.mask = 0xf
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}, {
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.num = 1,
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.pin = 23,
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.reg = 0x34,
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.bit = 8,
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.mask = 0xf
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}, {
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.num = 3,
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.pin = 12,
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.reg = 0x68,
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.bit = 8,
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.mask = 0xf
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}, {
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.num = 3,
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.pin = 13,
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.reg = 0x68,
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.bit = 12,
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.mask = 0xf
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}, {
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.num = 2,
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.pin = 2,
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.reg = 0x608,
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.bit = 0,
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.mask = 0x7
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}, {
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.num = 2,
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.pin = 3,
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.reg = 0x608,
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.bit = 4,
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.mask = 0x7
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}, {
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.num = 2,
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.pin = 16,
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.reg = 0x610,
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.bit = 8,
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.mask = 0x7
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}, {
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.num = 3,
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.pin = 10,
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.reg = 0x610,
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.bit = 0,
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.mask = 0x7
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}, {
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.num = 3,
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.pin = 11,
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.reg = 0x610,
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.bit = 4,
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.mask = 0x7
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},
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};
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static struct rockchip_mux_route_data rk3308_mux_route_data[] = {
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{
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/* rtc_clk */
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.bank_num = 0,
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.pin = 19,
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.func = 1,
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.route_offset = 0x314,
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.route_val = BIT(16 + 0) | BIT(0),
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}, {
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/* uart2_rxm0 */
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.bank_num = 1,
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.pin = 22,
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.func = 2,
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.route_offset = 0x314,
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.route_val = BIT(16 + 2) | BIT(16 + 3),
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}, {
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/* uart2_rxm1 */
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.bank_num = 4,
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.pin = 26,
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.func = 2,
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.route_offset = 0x314,
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.route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
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}, {
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/* i2c3_sdam0 */
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.bank_num = 0,
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.pin = 15,
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.func = 2,
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.route_offset = 0x608,
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.route_val = BIT(16 + 8) | BIT(16 + 9),
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}, {
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/* i2c3_sdam1 */
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.bank_num = 3,
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.pin = 12,
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.func = 2,
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.route_offset = 0x608,
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.route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(8),
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}, {
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/* i2c3_sdam2 */
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.bank_num = 2,
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.pin = 0,
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.func = 3,
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.route_offset = 0x608,
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.route_val = BIT(16 + 8) | BIT(16 + 9) | BIT(9),
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}, {
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/* i2s-8ch-1-sclktxm0 */
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.bank_num = 1,
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.pin = 3,
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.func = 2,
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.route_offset = 0x308,
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.route_val = BIT(16 + 3),
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}, {
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/* i2s-8ch-1-sclkrxm0 */
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.bank_num = 1,
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.pin = 4,
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.func = 2,
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.route_offset = 0x308,
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.route_val = BIT(16 + 3),
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}, {
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/* i2s-8ch-1-sclktxm1 */
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.bank_num = 1,
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.pin = 13,
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.func = 2,
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.route_offset = 0x308,
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.route_val = BIT(16 + 3) | BIT(3),
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}, {
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/* i2s-8ch-1-sclkrxm1 */
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.bank_num = 1,
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.pin = 14,
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.func = 2,
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.route_offset = 0x308,
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.route_val = BIT(16 + 3) | BIT(3),
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}, {
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/* pdm-clkm0 */
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.bank_num = 1,
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.pin = 4,
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.func = 3,
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.route_offset = 0x308,
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.route_val = BIT(16 + 12) | BIT(16 + 13),
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}, {
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/* pdm-clkm1 */
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.bank_num = 1,
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.pin = 14,
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.func = 4,
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.route_offset = 0x308,
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.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(12),
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}, {
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/* pdm-clkm2 */
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.bank_num = 2,
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.pin = 6,
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.func = 2,
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.route_offset = 0x308,
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.route_val = BIT(16 + 12) | BIT(16 + 13) | BIT(13),
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}, {
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/* pdm-clkm-m2 */
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.bank_num = 2,
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.pin = 4,
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.func = 3,
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.route_offset = 0x600,
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.route_val = BIT(16 + 2) | BIT(2),
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}, {
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/* spi1_miso */
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.bank_num = 3,
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.pin = 10,
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.func = 3,
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.route_offset = 0x314,
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.route_val = BIT(16 + 9),
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}, {
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/* spi1_miso_m1 */
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.bank_num = 2,
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.pin = 4,
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.func = 2,
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.route_offset = 0x314,
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.route_val = BIT(16 + 9) | BIT(9),
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}, {
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/* mac_rxd0_m0 */
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.bank_num = 1,
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.pin = 20,
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.func = 3,
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.route_offset = 0x314,
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.route_val = BIT(16 + 14),
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}, {
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/* mac_rxd0_m1 */
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.bank_num = 4,
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.pin = 2,
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.func = 2,
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.route_offset = 0x314,
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.route_val = BIT(16 + 14) | BIT(14),
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}, {
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/* uart3_rx */
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.bank_num = 3,
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.pin = 12,
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.func = 4,
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.route_offset = 0x314,
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.route_val = BIT(16 + 15),
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}, {
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/* uart3_rx_m1 */
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.bank_num = 0,
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.pin = 17,
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.func = 3,
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.route_offset = 0x314,
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.route_val = BIT(16 + 15) | BIT(15),
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},
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};
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static int rk3308_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, ret, mask, mux_type;
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u8 bit;
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u32 data, route_reg, route_val;
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regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
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? priv->regmap_pmu : priv->regmap_base;
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/* get basic quadrupel of mux registers and the correct reg inside */
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mux_type = bank->iomux[iomux_num].type;
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reg = bank->iomux[iomux_num].offset;
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reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
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if (bank->recalced_mask & BIT(pin))
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rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
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if (bank->route_mask & BIT(pin)) {
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if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
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&route_val)) {
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ret = regmap_write(regmap, route_reg, route_val);
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if (ret)
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return ret;
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}
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}
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data = (mask << (bit + 16));
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data |= (mux & mask) << bit;
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3308_PULL_OFFSET 0xa0
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static void rk3308_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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*reg = RK3308_PULL_OFFSET;
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*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
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*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
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*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
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*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
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}
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static int rk3308_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct regmap *regmap;
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int reg, ret;
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u8 bit, type;
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u32 data;
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if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
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return -ENOTSUPP;
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rk3308_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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type = bank->pull_type[pin_num / 8];
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ret = rockchip_translate_pull_value(type, pull);
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if (ret < 0) {
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debug("unsupported pull setting %d\n", pull);
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return ret;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3308_DRV_GRF_OFFSET 0x100
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static void rk3308_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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*reg = RK3308_DRV_GRF_OFFSET;
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*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
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*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
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*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
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*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
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}
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static int rk3308_set_drive(struct rockchip_pin_bank *bank,
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int pin_num, int strength)
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{
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struct regmap *regmap;
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int reg, ret;
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u32 data;
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u8 bit;
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int type = bank->drv[pin_num / 8].drv_type;
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rk3308_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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ret = rockchip_translate_drive_value(type, strength);
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if (ret < 0) {
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debug("unsupported driver strength %d\n", strength);
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return ret;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RK3308_SCHMITT_PINS_PER_REG 8
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#define RK3308_SCHMITT_BANK_STRIDE 16
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#define RK3308_SCHMITT_GRF_OFFSET 0x1a0
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static int rk3308_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num,
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struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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*regmap = priv->regmap_base;
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*reg = RK3308_SCHMITT_GRF_OFFSET;
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*reg += bank->bank_num * RK3308_SCHMITT_BANK_STRIDE;
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*reg += ((pin_num / RK3308_SCHMITT_PINS_PER_REG) * 4);
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*bit = pin_num % RK3308_SCHMITT_PINS_PER_REG;
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return 0;
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}
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static int rk3308_set_schmitt(struct rockchip_pin_bank *bank,
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int pin_num, int enable)
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{
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struct regmap *regmap;
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int reg;
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u8 bit;
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u32 data;
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rk3308_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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/* enable the write to the equivalent lower bits */
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data = BIT(bit + 16) | (enable << bit);
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return regmap_write(regmap, reg, data);
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}
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static struct rockchip_pin_bank rk3308_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT),
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PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT),
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PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT),
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PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT),
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PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT,
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IOMUX_8WIDTH_2BIT),
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};
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static struct rockchip_pin_ctrl rk3308_pin_ctrl = {
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.pin_banks = rk3308_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3308_pin_banks),
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.grf_mux_offset = 0x0,
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.iomux_recalced = rk3308_mux_recalced_data,
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.niomux_recalced = ARRAY_SIZE(rk3308_mux_recalced_data),
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.iomux_routes = rk3308_mux_route_data,
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.niomux_routes = ARRAY_SIZE(rk3308_mux_route_data),
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.set_mux = rk3308_set_mux,
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.set_drive = rk3308_set_drive,
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.set_pull = rk3308_set_pull,
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.set_schmitt = rk3308_set_schmitt,
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};
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static const struct udevice_id rk3308_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rk3308-pinctrl",
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.data = (ulong)&rk3308_pin_ctrl
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},
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk3308) = {
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.name = "rockchip_rk3308_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3308_pinctrl_ids,
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.priv_auto = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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