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https://github.com/brain-hackers/u-boot-brain
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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
371 lines
8.8 KiB
C
371 lines
8.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <linux/bitops.h>
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#include "pinctrl-rockchip.h"
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static struct rockchip_mux_route_data px30_mux_route_data[] = {
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{
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/* cif-d2m0 */
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.bank_num = 2,
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.pin = 0,
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.func = 1,
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.route_offset = 0x184,
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.route_val = BIT(16 + 7),
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}, {
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/* cif-d2m1 */
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.bank_num = 3,
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.pin = 3,
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.func = 3,
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.route_offset = 0x184,
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.route_val = BIT(16 + 7) | BIT(7),
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}, {
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/* pdm-m0 */
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.bank_num = 3,
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.pin = 22,
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.func = 2,
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.route_offset = 0x184,
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.route_val = BIT(16 + 8),
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}, {
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/* pdm-m1 */
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.bank_num = 2,
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.pin = 22,
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.func = 1,
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.route_offset = 0x184,
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.route_val = BIT(16 + 8) | BIT(8),
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}, {
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/* uart2-rxm0 */
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.bank_num = 1,
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.pin = 27,
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.func = 2,
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.route_offset = 0x184,
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.route_val = BIT(16 + 10),
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}, {
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/* uart2-rxm1 */
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.bank_num = 2,
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.pin = 14,
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.func = 2,
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.route_offset = 0x184,
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.route_val = BIT(16 + 10) | BIT(10),
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}, {
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/* uart3-rxm0 */
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.bank_num = 0,
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.pin = 17,
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.func = 2,
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.route_offset = 0x184,
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.route_val = BIT(16 + 9),
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}, {
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/* uart3-rxm1 */
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.bank_num = 1,
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.pin = 15,
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.func = 2,
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.route_offset = 0x184,
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.route_val = BIT(16 + 9) | BIT(9),
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},
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};
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static int px30_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, ret, mask, mux_type;
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u8 bit;
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u32 data, route_reg, route_val;
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regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
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? priv->regmap_pmu : priv->regmap_base;
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/* get basic quadrupel of mux registers and the correct reg inside */
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mux_type = bank->iomux[iomux_num].type;
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reg = bank->iomux[iomux_num].offset;
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reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
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if (bank->route_mask & BIT(pin)) {
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if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
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&route_val)) {
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ret = regmap_write(regmap, route_reg, route_val);
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if (ret)
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return ret;
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}
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}
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data = (mask << (bit + 16));
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data |= (mux & mask) << bit;
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define PX30_PULL_PMU_OFFSET 0x10
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#define PX30_PULL_GRF_OFFSET 0x60
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#define PX30_PULL_BITS_PER_PIN 2
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#define PX30_PULL_PINS_PER_REG 8
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#define PX30_PULL_BANK_STRIDE 16
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static void px30_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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/* The first 32 pins of the first bank are located in PMU */
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if (bank->bank_num == 0) {
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*regmap = priv->regmap_pmu;
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*reg = PX30_PULL_PMU_OFFSET;
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} else {
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*regmap = priv->regmap_base;
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*reg = PX30_PULL_GRF_OFFSET;
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/* correct the offset, as we're starting with the 2nd bank */
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*reg -= 0x10;
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*reg += bank->bank_num * PX30_PULL_BANK_STRIDE;
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}
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*reg += ((pin_num / PX30_PULL_PINS_PER_REG) * 4);
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*bit = (pin_num % PX30_PULL_PINS_PER_REG);
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*bit *= PX30_PULL_BITS_PER_PIN;
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}
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static int px30_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct regmap *regmap;
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int reg, ret;
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u8 bit, type;
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u32 data;
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if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
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return -ENOTSUPP;
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px30_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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type = bank->pull_type[pin_num / 8];
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ret = rockchip_translate_pull_value(type, pull);
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if (ret < 0) {
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debug("unsupported pull setting %d\n", pull);
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return ret;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define PX30_DRV_PMU_OFFSET 0x20
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#define PX30_DRV_GRF_OFFSET 0xf0
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#define PX30_DRV_BITS_PER_PIN 2
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#define PX30_DRV_PINS_PER_REG 8
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#define PX30_DRV_BANK_STRIDE 16
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static void px30_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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/* The first 32 pins of the first bank are located in PMU */
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if (bank->bank_num == 0) {
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*regmap = priv->regmap_pmu;
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*reg = PX30_DRV_PMU_OFFSET;
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} else {
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*regmap = priv->regmap_base;
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*reg = PX30_DRV_GRF_OFFSET;
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/* correct the offset, as we're starting with the 2nd bank */
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*reg -= 0x10;
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*reg += bank->bank_num * PX30_DRV_BANK_STRIDE;
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}
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*reg += ((pin_num / PX30_DRV_PINS_PER_REG) * 4);
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*bit = (pin_num % PX30_DRV_PINS_PER_REG);
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*bit *= PX30_DRV_BITS_PER_PIN;
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}
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static int px30_set_drive(struct rockchip_pin_bank *bank,
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int pin_num, int strength)
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{
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struct regmap *regmap;
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int reg, ret;
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u32 data, rmask_bits, temp;
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u8 bit;
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int drv_type = bank->drv[pin_num / 8].drv_type;
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px30_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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ret = rockchip_translate_drive_value(drv_type, strength);
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if (ret < 0) {
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debug("unsupported driver strength %d\n", strength);
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return ret;
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}
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switch (drv_type) {
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case DRV_TYPE_IO_1V8_3V0_AUTO:
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case DRV_TYPE_IO_3V3_ONLY:
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rmask_bits = ROCKCHIP_DRV_3BITS_PER_PIN;
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switch (bit) {
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case 0 ... 12:
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/* regular case, nothing to do */
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break;
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case 15:
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/*
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* drive-strength offset is special, as it is spread
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* over 2 registers, the bit data[15] contains bit 0
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* of the value while temp[1:0] contains bits 2 and 1
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*/
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data = (ret & 0x1) << 15;
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temp = (ret >> 0x1) & 0x3;
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data |= BIT(31);
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ret = regmap_write(regmap, reg, data);
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if (ret)
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return ret;
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temp |= (0x3 << 16);
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reg += 0x4;
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ret = regmap_write(regmap, reg, temp);
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return ret;
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case 18 ... 21:
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/* setting fully enclosed in the second register */
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reg += 4;
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bit -= 16;
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break;
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default:
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debug("unsupported bit: %d for pinctrl drive type: %d\n",
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bit, drv_type);
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return -EINVAL;
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}
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break;
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case DRV_TYPE_IO_DEFAULT:
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case DRV_TYPE_IO_1V8_OR_3V0:
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case DRV_TYPE_IO_1V8_ONLY:
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rmask_bits = ROCKCHIP_DRV_BITS_PER_PIN;
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break;
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default:
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debug("unsupported pinctrl drive type: %d\n",
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drv_type);
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return -EINVAL;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << rmask_bits) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define PX30_SCHMITT_PMU_OFFSET 0x38
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#define PX30_SCHMITT_GRF_OFFSET 0xc0
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#define PX30_SCHMITT_PINS_PER_PMU_REG 16
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#define PX30_SCHMITT_BANK_STRIDE 16
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#define PX30_SCHMITT_PINS_PER_GRF_REG 8
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static int px30_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num,
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struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int pins_per_reg;
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if (bank->bank_num == 0) {
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*regmap = priv->regmap_pmu;
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*reg = PX30_SCHMITT_PMU_OFFSET;
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pins_per_reg = PX30_SCHMITT_PINS_PER_PMU_REG;
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} else {
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*regmap = priv->regmap_base;
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*reg = PX30_SCHMITT_GRF_OFFSET;
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pins_per_reg = PX30_SCHMITT_PINS_PER_GRF_REG;
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*reg += (bank->bank_num - 1) * PX30_SCHMITT_BANK_STRIDE;
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}
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*reg += ((pin_num / pins_per_reg) * 4);
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*bit = pin_num % pins_per_reg;
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return 0;
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}
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static int px30_set_schmitt(struct rockchip_pin_bank *bank,
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int pin_num, int enable)
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{
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struct regmap *regmap;
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int reg;
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u8 bit;
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u32 data;
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px30_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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/* enable the write to the equivalent lower bits */
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data = BIT(bit + 16) | (enable << bit);
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return regmap_write(regmap, reg, data);
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}
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static struct rockchip_pin_bank px30_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU
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),
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PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT
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),
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PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT
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),
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PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT
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),
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};
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static struct rockchip_pin_ctrl px30_pin_ctrl = {
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.pin_banks = px30_pin_banks,
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.nr_banks = ARRAY_SIZE(px30_pin_banks),
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.grf_mux_offset = 0x0,
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.pmu_mux_offset = 0x0,
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.grf_drv_offset = 0xf0,
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.pmu_drv_offset = 0x20,
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.iomux_routes = px30_mux_route_data,
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.niomux_routes = ARRAY_SIZE(px30_mux_route_data),
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.set_mux = px30_set_mux,
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.set_pull = px30_set_pull,
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.set_drive = px30_set_drive,
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.set_schmitt = px30_set_schmitt,
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};
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static const struct udevice_id px30_pinctrl_ids[] = {
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{
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.compatible = "rockchip,px30-pinctrl",
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.data = (ulong)&px30_pin_ctrl
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},
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{ }
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};
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U_BOOT_DRIVER(pinctrl_px30) = {
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.name = "rockchip_px30_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = px30_pinctrl_ids,
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.priv_auto = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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