mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
8d393b2c22
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - livetree API (dev_read_...) is used instead of fdt one (fdt...). - doc/device-tree-bindings/pinctrl/nexell,s5pxx18-pinctrl.txt added. Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
69 lines
1.7 KiB
C
69 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0+
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*
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* Pinctrl driver for Nexell SoCs
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* (C) Copyright 2016 Nexell
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* Bongyu, KOO <freestyle@nexell.co.kr>
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*
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*/
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#ifndef __PINCTRL_NEXELL_H_
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#define __PINCTRL_NEXELL_H_
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/**
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* struct nexell_pin_bank_data: represent a controller pin-bank data.
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* @offset: starting offset of the pin-bank registers.
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* @nr_pins: number of pins included in this bank.
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* @name: name to be prefixed for each pin in this pin bank.
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*/
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struct nexell_pin_bank_data {
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u32 offset;
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u8 nr_pins;
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const char *name;
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u8 type;
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};
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#define NEXELL_PIN_BANK(pins, reg, id) \
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{ \
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.offset = reg, \
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.nr_pins = pins, \
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.name = id \
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}
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/**
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* struct nexell_pin_ctrl: represent a pin controller.
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* @pin_banks: list of pin banks included in this controller.
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* @nr_banks: number of pin banks.
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*/
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struct nexell_pin_ctrl {
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const struct nexell_pin_bank_data *pin_banks;
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u32 nr_banks;
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};
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/**
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* struct nexell_pinctrl_priv: nexell pin controller driver private data
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* @pin_ctrl: pin controller bank information.
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* @base: base address of the pin controller instance.
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*/
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struct nexell_pinctrl_priv {
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const struct nexell_pin_ctrl *pin_ctrl;
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unsigned long base;
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};
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/**
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* struct nexell_pinctrl_config_data: configuration for a peripheral.
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* @offset: offset of the config registers in the controller.
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* @mask: value of the register to be masked with.
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* @value: new value to be programmed.
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*/
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struct nexell_pinctrl_config_data {
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const unsigned int offset;
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const unsigned int mask;
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const unsigned int value;
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};
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unsigned long pin_to_bank_base(struct udevice *dev, const char *pin_name,
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u32 *pin);
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int nexell_pinctrl_probe(struct udevice *dev);
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#endif /* __PINCTRL_NEXELL_H_ */
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