160 lines
3.6 KiB
C
160 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Stefan Roese <sr@denx.de>
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*/
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <log.h>
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#include <pci.h>
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#include <linux/delay.h>
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#include <mach/octeon-model.h>
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#include <mach/octeon_pci.h>
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#include <mach/cvmx-regs.h>
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#include <mach/cvmx-pcie.h>
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#include <mach/cvmx-pemx-defs.h>
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struct octeon_pcie {
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void *base;
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int first_busno;
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u32 port;
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struct udevice *dev;
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int pcie_port;
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};
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static bool octeon_bdf_invalid(pci_dev_t bdf, int first_busno)
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{
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/*
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* In PCIe only a single device (0) can exist on the local bus.
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* Beyound the local bus, there might be a switch and everything
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* is possible.
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*/
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if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
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return true;
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return false;
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}
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static int pcie_octeon_write_config(struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong value,
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enum pci_size_t size)
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{
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struct octeon_pcie *pcie = dev_get_priv(bus);
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struct pci_controller *hose = dev_get_uclass_priv(bus);
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int busno;
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int port;
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debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
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debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value);
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port = pcie->pcie_port;
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busno = PCI_BUS(bdf) - hose->first_busno + 1;
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switch (size) {
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case PCI_SIZE_8:
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cvmx_pcie_config_write8(port, busno, PCI_DEV(bdf),
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PCI_FUNC(bdf), offset, value);
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break;
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case PCI_SIZE_16:
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cvmx_pcie_config_write16(port, busno, PCI_DEV(bdf),
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PCI_FUNC(bdf), offset, value);
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break;
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case PCI_SIZE_32:
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cvmx_pcie_config_write32(port, busno, PCI_DEV(bdf),
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PCI_FUNC(bdf), offset, value);
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break;
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default:
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printf("Invalid size\n");
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};
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return 0;
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}
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static int pcie_octeon_read_config(const struct udevice *bus, pci_dev_t bdf,
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uint offset, ulong *valuep,
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enum pci_size_t size)
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{
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struct octeon_pcie *pcie = dev_get_priv(bus);
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struct pci_controller *hose = dev_get_uclass_priv(bus);
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int busno;
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int port;
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port = pcie->pcie_port;
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busno = PCI_BUS(bdf) - hose->first_busno + 1;
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if (octeon_bdf_invalid(bdf, pcie->first_busno)) {
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*valuep = pci_get_ff(size);
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return 0;
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}
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switch (size) {
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case PCI_SIZE_8:
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*valuep = cvmx_pcie_config_read8(port, busno, PCI_DEV(bdf),
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PCI_FUNC(bdf), offset);
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break;
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case PCI_SIZE_16:
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*valuep = cvmx_pcie_config_read16(port, busno, PCI_DEV(bdf),
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PCI_FUNC(bdf), offset);
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break;
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case PCI_SIZE_32:
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*valuep = cvmx_pcie_config_read32(port, busno, PCI_DEV(bdf),
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PCI_FUNC(bdf), offset);
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break;
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default:
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printf("Invalid size\n");
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};
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debug("%02x.%02x.%02x: u%d %x -> %lx\n",
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PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), size, offset, *valuep);
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return 0;
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}
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static int pcie_octeon_probe(struct udevice *dev)
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{
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struct octeon_pcie *pcie = dev_get_priv(dev);
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int node = cvmx_get_node_num();
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int pcie_port;
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int ret = 0;
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/* Get port number, lane number and memory target / attr */
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if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port",
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&pcie->port)) {
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ret = -ENODEV;
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goto err;
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}
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pcie->first_busno = dev_seq(dev);
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pcie_port = ((node << 4) | pcie->port);
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ret = cvmx_pcie_rc_initialize(pcie_port);
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if (ret != 0)
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return ret;
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return 0;
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err:
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return ret;
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}
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static const struct dm_pci_ops pcie_octeon_ops = {
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.read_config = pcie_octeon_read_config,
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.write_config = pcie_octeon_write_config,
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};
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static const struct udevice_id pcie_octeon_ids[] = {
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{ .compatible = "marvell,pcie-host-octeon" },
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{ }
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};
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U_BOOT_DRIVER(pcie_octeon) = {
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.name = "pcie_octeon",
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.id = UCLASS_PCI,
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.of_match = pcie_octeon_ids,
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.ops = &pcie_octeon_ops,
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.probe = pcie_octeon_probe,
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.priv_auto = sizeof(struct octeon_pcie),
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.flags = DM_FLAG_PRE_RELOC,
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};
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