150 lines
3.9 KiB
C
150 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017-2020 NXP
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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* Layerscape PCIe driver
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*/
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#include <common.h>
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#include <log.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <malloc.h>
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#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
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defined(CONFIG_ARM)
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#include <asm/arch/clock.h>
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#endif
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#include "pcie_layerscape.h"
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DECLARE_GLOBAL_DATA_PTR;
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LIST_HEAD(ls_pcie_list);
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unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)
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{
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return in_le32(pcie->dbi + offset);
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}
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void dbi_writel(struct ls_pcie *pcie, unsigned int value, unsigned int offset)
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{
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out_le32(pcie->dbi + offset, value);
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}
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unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset)
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{
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if (pcie->big_endian)
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return in_be32(pcie->ctrl + offset);
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else
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return in_le32(pcie->ctrl + offset);
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}
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void ctrl_writel(struct ls_pcie *pcie, unsigned int value,
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unsigned int offset)
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{
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if (pcie->big_endian)
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out_be32(pcie->ctrl + offset, value);
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else
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out_le32(pcie->ctrl + offset, value);
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}
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void ls_pcie_dbi_ro_wr_en(struct ls_pcie *pcie)
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{
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u32 reg, val;
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reg = PCIE_MISC_CONTROL_1_OFF;
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val = dbi_readl(pcie, reg);
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val |= PCIE_DBI_RO_WR_EN;
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dbi_writel(pcie, val, reg);
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}
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void ls_pcie_dbi_ro_wr_dis(struct ls_pcie *pcie)
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{
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u32 reg, val;
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reg = PCIE_MISC_CONTROL_1_OFF;
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val = dbi_readl(pcie, reg);
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val &= ~PCIE_DBI_RO_WR_EN;
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dbi_writel(pcie, val, reg);
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}
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static int ls_pcie_ltssm(struct ls_pcie *pcie)
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{
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u32 state;
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uint svr;
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svr = get_svr();
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if (((svr >> SVR_VAR_PER_SHIFT) & SVR_LS102XA_MASK) == SVR_LS102XA) {
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state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx));
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state = (state >> LS1021_LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
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} else {
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state = ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK;
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}
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return state;
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}
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int ls_pcie_link_up(struct ls_pcie *pcie)
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{
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int ltssm;
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ltssm = ls_pcie_ltssm(pcie);
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if (ltssm < LTSSM_PCIE_L0)
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return 0;
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return 1;
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}
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void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type,
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u64 phys, u64 bus_addr, u64 size)
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{
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dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT);
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dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE);
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dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE);
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dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT);
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dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET);
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dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET);
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dbi_writel(pcie, type, PCIE_ATU_CR1);
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dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
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}
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/* Use bar match mode and MEM type as default */
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void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, u32 pf, u32 vf_flag,
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int type, int idx, int bar, u64 phys)
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{
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dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT);
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dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET);
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dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET);
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dbi_writel(pcie, type | PCIE_ATU_FUNC_NUM(pf), PCIE_ATU_CR1);
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dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
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(vf_flag ? PCIE_ATU_FUNC_NUM_MATCH_EN : 0) |
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(vf_flag ? PCIE_ATU_VFBAR_MATCH_MODE_EN : 0) |
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PCIE_ATU_BAR_NUM(bar), PCIE_ATU_CR2);
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}
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void ls_pcie_dump_atu(struct ls_pcie *pcie, u32 win_num, u32 type)
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{
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int win_idx;
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for (win_idx = 0; win_idx < win_num; win_idx++) {
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dbi_writel(pcie, type | win_idx, PCIE_ATU_VIEWPORT);
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debug("iATU%d:\n", win_idx);
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debug("\tLOWER PHYS 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_LOWER_BASE));
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debug("\tUPPER PHYS 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_UPPER_BASE));
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if (type == PCIE_ATU_REGION_OUTBOUND) {
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debug("\tLOWER BUS 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_LOWER_TARGET));
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debug("\tUPPER BUS 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_UPPER_TARGET));
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debug("\tLIMIT 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_LIMIT));
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}
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debug("\tCR1 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_CR1));
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debug("\tCR2 0x%08x\n",
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dbi_readl(pcie, PCIE_ATU_CR2));
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}
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}
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