508 lines
12 KiB
C
508 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* SiFive FU740 DesignWare PCIe Controller
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*
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* Copyright (C) 2020-2021 SiFive, Inc.
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*
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* Based in early part on the i.MX6 PCIe host controller shim which is:
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*
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* Copyright (C) 2013 Kosagi
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* http://www.kosagi.com
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*
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* Based on driver from author: Alan Mikhak <amikhak@wirelessfabric.com>
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*/
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#include <asm/io.h>
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#include <asm-generic/gpio.h>
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <generic-phy.h>
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#include <linux/bitops.h>
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#include <linux/log2.h>
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#include <pci.h>
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#include <pci_ep.h>
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#include <pci_ids.h>
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#include <regmap.h>
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#include <reset.h>
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#include <syscon.h>
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#include "pcie_dw_common.h"
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struct pcie_sifive {
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/* Must be first member of the struct */
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struct pcie_dw dw;
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/* private control regs */
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void __iomem *priv_base;
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/* reset, power, clock resources */
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int sys_int_pin;
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struct gpio_desc pwren_gpio;
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struct gpio_desc reset_gpio;
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struct clk aux_ck;
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struct reset_ctl reset;
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};
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enum pcie_sifive_devtype {
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SV_PCIE_UNKNOWN_TYPE = 0,
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SV_PCIE_ENDPOINT_TYPE = 1,
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SV_PCIE_HOST_TYPE = 3
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};
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#define ASSERTION_DELAY 100
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#define PCIE_PERST_ASSERT 0x0
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#define PCIE_PERST_DEASSERT 0x1
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#define PCIE_PHY_RESET 0x1
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#define PCIE_PHY_RESET_DEASSERT 0x0
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#define GPIO_LOW 0x0
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#define GPIO_HIGH 0x1
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#define PCIE_PHY_SEL 0x1
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#define sv_info(sv, fmt, arg...) printf(fmt, ## arg)
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#define sv_warn(sv, fmt, arg...) printf(fmt, ## arg)
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#define sv_debug(sv, fmt, arg...) debug(fmt, ## arg)
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#define sv_err(sv, fmt, arg...) printf(fmt, ## arg)
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/* Doorbell Interface */
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#define DBI_OFFSET 0x0
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#define DBI_SIZE 0x1000
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#define PL_OFFSET 0x700
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#define PHY_DEBUG_R0 (PL_OFFSET + 0x28)
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#define PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
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#define PHY_DEBUG_R1_LINK_UP (0x1 << 4)
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#define PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
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#define PCIE_MISC_CONTROL_1 0x8bc
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#define DBI_RO_WR_EN BIT(0)
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/* pcie reset */
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#define PCIEX8MGMT_PERST_N 0x0
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/* LTSSM */
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#define PCIEX8MGMT_APP_LTSSM_ENABLE 0x10
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#define LTSSM_ENABLE_BIT BIT(0)
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/* phy reset */
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#define PCIEX8MGMT_APP_HOLD_PHY_RST 0x18
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/* device type */
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#define PCIEX8MGMT_DEVICE_TYPE 0x708
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#define DEVICE_TYPE_EP 0x0
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#define DEVICE_TYPE_RC 0x4
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/* phy control registers*/
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#define PCIEX8MGMT_PHY0_CR_PARA_ADDR 0x860
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#define PCIEX8MGMT_PHY0_CR_PARA_RD_EN 0x870
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#define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA 0x878
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#define PCIEX8MGMT_PHY0_CR_PARA_SEL 0x880
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#define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA 0x888
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#define PCIEX8MGMT_PHY0_CR_PARA_WR_EN 0x890
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#define PCIEX8MGMT_PHY0_CR_PARA_ACK 0x898
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#define PCIEX8MGMT_PHY1_CR_PARA_ADDR 0x8a0
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#define PCIEX8MGMT_PHY1_CR_PARA_RD_EN 0x8b0
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#define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA 0x8b8
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#define PCIEX8MGMT_PHY1_CR_PARA_SEL 0x8c0
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#define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA 0x8c8
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#define PCIEX8MGMT_PHY1_CR_PARA_WR_EN 0x8d0
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#define PCIEX8MGMT_PHY1_CR_PARA_ACK 0x8d8
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#define PCIEX8MGMT_LANE_NUM 8
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#define PCIEX8MGMT_LANE 0x1008
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#define PCIEX8MGMT_LANE_OFF 0x100
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#define PCIEX8MGMT_TERM_MODE 0x0e21
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#define PCIE_CAP_BASE 0x70
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#define PCI_CONFIG(r) (DBI_OFFSET + (r))
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#define PCIE_CAPABILITIES(r) PCI_CONFIG(PCIE_CAP_BASE + (r))
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/* Link capability */
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#define PF0_PCIE_CAP_LINK_CAP PCIE_CAPABILITIES(0xc)
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#define PCIE_LINK_CAP_MAX_SPEED_MASK 0xf
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#define PCIE_LINK_CAP_MAX_SPEED_GEN1 BIT(0)
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#define PCIE_LINK_CAP_MAX_SPEED_GEN2 BIT(1)
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#define PCIE_LINK_CAP_MAX_SPEED_GEN3 BIT(2)
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#define PCIE_LINK_CAP_MAX_SPEED_GEN4 BIT(3)
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static enum pcie_sifive_devtype pcie_sifive_get_devtype(struct pcie_sifive *sv)
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{
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u32 val;
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val = readl(sv->priv_base + PCIEX8MGMT_DEVICE_TYPE);
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switch (val) {
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case DEVICE_TYPE_RC:
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return SV_PCIE_HOST_TYPE;
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case DEVICE_TYPE_EP:
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return SV_PCIE_ENDPOINT_TYPE;
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default:
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return SV_PCIE_UNKNOWN_TYPE;
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}
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}
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static void pcie_sifive_priv_set_state(struct pcie_sifive *sv, u32 reg,
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u32 bits, int state)
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{
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u32 val;
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val = readl(sv->priv_base + reg);
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val = state ? (val | bits) : (val & !bits);
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writel(val, sv->priv_base + reg);
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}
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static void pcie_sifive_assert_reset(struct pcie_sifive *sv)
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{
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dm_gpio_set_value(&sv->reset_gpio, GPIO_LOW);
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writel(PCIE_PERST_ASSERT, sv->priv_base + PCIEX8MGMT_PERST_N);
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mdelay(ASSERTION_DELAY);
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}
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static void pcie_sifive_power_on(struct pcie_sifive *sv)
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{
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dm_gpio_set_value(&sv->pwren_gpio, GPIO_HIGH);
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mdelay(ASSERTION_DELAY);
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}
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static void pcie_sifive_deassert_reset(struct pcie_sifive *sv)
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{
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writel(PCIE_PERST_DEASSERT, sv->priv_base + PCIEX8MGMT_PERST_N);
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dm_gpio_set_value(&sv->reset_gpio, GPIO_HIGH);
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mdelay(ASSERTION_DELAY);
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}
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static int pcie_sifive_setphy(const u8 phy, const u8 write,
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const u16 addr, const u16 wrdata,
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u16 *rddata, struct pcie_sifive *sv)
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{
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unsigned char ack = 0;
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if (!(phy == 0 || phy == 1))
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return -2;
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/* setup phy para */
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writel(addr, sv->priv_base +
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(phy ? PCIEX8MGMT_PHY1_CR_PARA_ADDR :
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PCIEX8MGMT_PHY0_CR_PARA_ADDR));
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if (write)
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writel(wrdata, sv->priv_base +
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(phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_DATA :
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PCIEX8MGMT_PHY0_CR_PARA_WR_DATA));
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/* enable access if write */
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if (write)
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writel(1, sv->priv_base +
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(phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_EN :
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PCIEX8MGMT_PHY0_CR_PARA_WR_EN));
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else
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writel(1, sv->priv_base +
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(phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_EN :
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PCIEX8MGMT_PHY0_CR_PARA_RD_EN));
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/* wait for wait_idle */
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do {
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u32 val;
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val = readl(sv->priv_base +
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(phy ? PCIEX8MGMT_PHY1_CR_PARA_ACK :
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PCIEX8MGMT_PHY0_CR_PARA_ACK));
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if (val) {
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ack = 1;
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if (!write)
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readl(sv->priv_base +
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(phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_DATA :
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PCIEX8MGMT_PHY0_CR_PARA_RD_DATA));
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mdelay(1);
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}
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} while (!ack);
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/* clear */
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if (write)
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writel(0, sv->priv_base +
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(phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_EN :
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PCIEX8MGMT_PHY0_CR_PARA_WR_EN));
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else
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writel(0, sv->priv_base +
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(phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_EN :
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PCIEX8MGMT_PHY0_CR_PARA_RD_EN));
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while (readl(sv->priv_base +
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(phy ? PCIEX8MGMT_PHY1_CR_PARA_ACK :
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PCIEX8MGMT_PHY0_CR_PARA_ACK))) {
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/* wait for ~wait_idle */
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}
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return 0;
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}
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static void pcie_sifive_init_phy(struct pcie_sifive *sv)
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{
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int lane;
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/* enable phy cr_para_sel interfaces */
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writel(PCIE_PHY_SEL, sv->priv_base + PCIEX8MGMT_PHY0_CR_PARA_SEL);
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writel(PCIE_PHY_SEL, sv->priv_base + PCIEX8MGMT_PHY1_CR_PARA_SEL);
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mdelay(1);
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/* set PHY AC termination mode */
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for (lane = 0; lane < PCIEX8MGMT_LANE_NUM; lane++) {
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pcie_sifive_setphy(0, 1,
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PCIEX8MGMT_LANE +
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(PCIEX8MGMT_LANE_OFF * lane),
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PCIEX8MGMT_TERM_MODE, NULL, sv);
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pcie_sifive_setphy(1, 1,
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PCIEX8MGMT_LANE +
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(PCIEX8MGMT_LANE_OFF * lane),
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PCIEX8MGMT_TERM_MODE, NULL, sv);
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}
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}
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static int pcie_sifive_check_link(struct pcie_sifive *sv)
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{
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u32 val;
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val = readl(sv->dw.dbi_base + PHY_DEBUG_R1);
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return (val & PHY_DEBUG_R1_LINK_UP) &&
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!(val & PHY_DEBUG_R1_LINK_IN_TRAINING);
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}
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static void pcie_sifive_force_gen1(struct pcie_sifive *sv)
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{
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u32 val, linkcap;
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/*
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* Force Gen1 operation when starting the link. In case the link is
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* started in Gen2 mode, there is a possibility the devices on the
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* bus will not be detected at all. This happens with PCIe switches.
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*/
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/* ctrl_ro_wr_enable */
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val = readl(sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
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val |= DBI_RO_WR_EN;
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writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
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/* configure link cap */
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linkcap = readl(sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP);
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linkcap |= PCIE_LINK_CAP_MAX_SPEED_MASK;
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writel(linkcap, sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP);
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/* ctrl_ro_wr_disable */
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val &= ~DBI_RO_WR_EN;
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writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
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}
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static void pcie_sifive_print_phy_debug(struct pcie_sifive *sv)
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{
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sv_err(sv, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
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readl(sv->dw.dbi_base + PHY_DEBUG_R0),
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readl(sv->dw.dbi_base + PHY_DEBUG_R1));
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}
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static int pcie_sifive_wait_for_link(struct pcie_sifive *sv)
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{
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u32 val;
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int timeout;
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/* Wait for the link to train */
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mdelay(20);
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timeout = 20;
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do {
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mdelay(1);
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} while (--timeout && !pcie_sifive_check_link(sv));
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val = readl(sv->dw.dbi_base + PHY_DEBUG_R1);
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if (!(val & PHY_DEBUG_R1_LINK_UP) ||
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(val & PHY_DEBUG_R1_LINK_IN_TRAINING)) {
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sv_info(sv, "Failed to negotiate PCIe link!\n");
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pcie_sifive_print_phy_debug(sv);
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writel(PCIE_PHY_RESET,
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sv->priv_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int pcie_sifive_start_link(struct pcie_sifive *sv)
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{
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if (pcie_sifive_check_link(sv))
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return -EALREADY;
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pcie_sifive_force_gen1(sv);
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/* set ltssm */
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pcie_sifive_priv_set_state(sv, PCIEX8MGMT_APP_LTSSM_ENABLE,
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LTSSM_ENABLE_BIT, 1);
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return 0;
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}
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static int pcie_sifive_init_port(struct udevice *dev,
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enum pcie_sifive_devtype mode)
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{
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struct pcie_sifive *sv = dev_get_priv(dev);
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int ret;
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/* Power on reset */
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pcie_sifive_assert_reset(sv);
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pcie_sifive_power_on(sv);
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pcie_sifive_deassert_reset(sv);
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/* Enable pcieauxclk */
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ret = clk_enable(&sv->aux_ck);
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if (ret)
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dev_err(dev, "unable to enable pcie_aux clock\n");
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/*
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* assert hold_phy_rst (hold the controller LTSSM in reset
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* after power_up_rst_n for register programming with cr_para)
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*/
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writel(PCIE_PHY_RESET, sv->priv_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
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/* deassert power_up_rst_n */
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ret = reset_deassert(&sv->reset);
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if (ret < 0) {
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dev_err(dev, "failed to deassert reset");
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return -EINVAL;
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}
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pcie_sifive_init_phy(sv);
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/* disable pcieauxclk */
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clk_disable(&sv->aux_ck);
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/* deassert hold_phy_rst */
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writel(PCIE_PHY_RESET_DEASSERT,
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sv->priv_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
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/* enable pcieauxclk */
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clk_enable(&sv->aux_ck);
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/* Set desired mode while core is not operational */
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if (mode == SV_PCIE_HOST_TYPE)
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writel(DEVICE_TYPE_RC,
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sv->priv_base + PCIEX8MGMT_DEVICE_TYPE);
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else
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writel(DEVICE_TYPE_EP,
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sv->priv_base + PCIEX8MGMT_DEVICE_TYPE);
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/* Confirm desired mode from operational core */
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if (pcie_sifive_get_devtype(sv) != mode)
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return -EINVAL;
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pcie_dw_setup_host(&sv->dw);
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if (pcie_sifive_start_link(sv) == -EALREADY)
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sv_info(sv, "PCIe link is already up\n");
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else if (pcie_sifive_wait_for_link(sv) == -ETIMEDOUT)
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return -ETIMEDOUT;
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return 0;
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}
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static int pcie_sifive_probe(struct udevice *dev)
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{
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struct pcie_sifive *sv = dev_get_priv(dev);
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struct udevice *parent = pci_get_controller(dev);
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struct pci_controller *hose = dev_get_uclass_priv(parent);
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int err;
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sv->dw.first_busno = dev_seq(dev);
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sv->dw.dev = dev;
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err = pcie_sifive_init_port(dev, SV_PCIE_HOST_TYPE);
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if (err) {
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sv_info(sv, "Failed to init port.\n");
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return err;
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}
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printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
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dev_seq(dev), pcie_dw_get_link_speed(&sv->dw),
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pcie_dw_get_link_width(&sv->dw),
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hose->first_busno);
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return pcie_dw_prog_outbound_atu_unroll(&sv->dw,
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PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_MEM,
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sv->dw.mem.phys_start,
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sv->dw.mem.bus_start,
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sv->dw.mem.size);
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}
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static void __iomem *get_fdt_addr(struct udevice *dev, const char *name)
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{
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fdt_addr_t addr;
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addr = dev_read_addr_name(dev, name);
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return (addr == FDT_ADDR_T_NONE) ? NULL : (void __iomem *)addr;
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}
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static int pcie_sifive_of_to_plat(struct udevice *dev)
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{
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struct pcie_sifive *sv = dev_get_priv(dev);
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int err;
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/* get designware DBI base addr */
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sv->dw.dbi_base = get_fdt_addr(dev, "dbi");
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if (!sv->dw.dbi_base)
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return -EINVAL;
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/* get private control base addr */
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sv->priv_base = get_fdt_addr(dev, "mgmt");
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if (!sv->priv_base)
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return -EINVAL;
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gpio_request_by_name(dev, "pwren-gpios", 0, &sv->pwren_gpio,
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GPIOD_IS_OUT);
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if (!dm_gpio_is_valid(&sv->pwren_gpio)) {
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sv_info(sv, "pwren_gpio is invalid\n");
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return -EINVAL;
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}
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gpio_request_by_name(dev, "reset-gpios", 0, &sv->reset_gpio,
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GPIOD_IS_OUT);
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if (!dm_gpio_is_valid(&sv->reset_gpio)) {
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sv_info(sv, "reset_gpio is invalid\n");
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return -EINVAL;
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}
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|
|
|
err = clk_get_by_index(dev, 0, &sv->aux_ck);
|
|
if (err) {
|
|
sv_info(sv, "clk_get_by_index(aux_ck) failed: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
err = reset_get_by_index(dev, 0, &sv->reset);
|
|
if (err) {
|
|
sv_info(sv, "reset_get_by_index(reset) failed: %d\n", err);
|
|
return err;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_pci_ops pcie_sifive_ops = {
|
|
.read_config = pcie_dw_read_config,
|
|
.write_config = pcie_dw_write_config,
|
|
};
|
|
|
|
static const struct udevice_id pcie_sifive_ids[] = {
|
|
{ .compatible = "sifive,fu740-pcie" },
|
|
{}
|
|
};
|
|
|
|
U_BOOT_DRIVER(pcie_sifive) = {
|
|
.name = "pcie_sifive",
|
|
.id = UCLASS_PCI,
|
|
.of_match = pcie_sifive_ids,
|
|
.ops = &pcie_sifive_ops,
|
|
.of_to_plat = pcie_sifive_of_to_plat,
|
|
.probe = pcie_sifive_probe,
|
|
.priv_auto = sizeof(struct pcie_sifive),
|
|
};
|