mirror of
https://github.com/brain-hackers/u-boot-brain
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4684a7a43a
Adds support for Network Interface controllers found on OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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/**
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* Atomically adds a signed value to a 64 bit (aligned) memory location,
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* and returns previous value.
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*
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* This version does not perform 'sync' operations to enforce memory
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* operations. This should only be used when there are no memory operation
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* ordering constraints. (This should NOT be used for reference counting -
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* use the standard version instead.)
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*
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* @param ptr address in memory to add incr to
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* @param incr amount to increment memory location by (signed)
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*
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* @return Value of memory location before increment
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*/
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static inline s64 atomic_fetch_and_add64_nosync(s64 *ptr, s64 incr)
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{
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s64 result;
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/* Atomic add with no ordering */
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asm volatile("ldadd %x[i], %x[r], [%[b]]"
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: [r] "=r" (result), "+m" (*ptr)
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: [i] "r" (incr), [b] "r" (ptr)
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: "memory");
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return result;
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}
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static inline void lmt_cancel(const struct nix *nix)
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{
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writeq(0, nix->lmt_base + LMT_LF_LMTCANCEL());
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}
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static inline u64 *lmt_store_ptr(struct nix *nix)
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{
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return (u64 *)((u8 *)(nix->lmt_base) +
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LMT_LF_LMTLINEX(0));
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}
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static inline s64 lmt_submit(u64 io_address)
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{
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s64 result = 0;
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asm volatile("ldeor xzr, %x[rf],[%[rs]]"
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: [rf] "=r"(result) : [rs] "r"(io_address));
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return result;
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}
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