150 lines
3.9 KiB
C
150 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2021 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <miiphy.h>
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#include <asm/io.h>
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#include <linux/bitfield.h>
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#define ETH_PLL_STS 0x40
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#define ETH_PLL_CTL0 0x44
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#define PLL_CTL0_LOCK_DIG BIT(30)
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#define PLL_CTL0_RST BIT(29)
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#define PLL_CTL0_EN BIT(28)
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#define PLL_CTL0_SEL BIT(23)
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#define PLL_CTL0_N GENMASK(14, 10)
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#define PLL_CTL0_M GENMASK(8, 0)
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#define PLL_LOCK_TIMEOUT 1000000
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#define PLL_MUX_NUM_PARENT 2
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#define ETH_PLL_CTL1 0x48
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#define ETH_PLL_CTL2 0x4c
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#define ETH_PLL_CTL3 0x50
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#define ETH_PLL_CTL4 0x54
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#define ETH_PLL_CTL5 0x58
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#define ETH_PLL_CTL6 0x5c
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#define ETH_PLL_CTL7 0x60
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#define ETH_PHY_CNTL0 0x80
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#define EPHY_G12A_ID 0x33010180
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#define ETH_PHY_CNTL1 0x84
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#define PHY_CNTL1_ST_MODE GENMASK(2, 0)
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#define PHY_CNTL1_ST_PHYADD GENMASK(7, 3)
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#define EPHY_DFLT_ADD 8
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#define PHY_CNTL1_MII_MODE GENMASK(15, 14)
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#define EPHY_MODE_RMII 0x1
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#define PHY_CNTL1_CLK_EN BIT(16)
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#define PHY_CNTL1_CLKFREQ BIT(17)
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#define PHY_CNTL1_PHY_ENB BIT(18)
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#define ETH_PHY_CNTL2 0x88
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#define PHY_CNTL2_USE_INTERNAL BIT(5)
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#define PHY_CNTL2_SMI_SRC_MAC BIT(6)
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#define PHY_CNTL2_RX_CLK_EPHY BIT(9)
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#define MESON_G12A_MDIO_EXTERNAL_ID 0
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#define MESON_G12A_MDIO_INTERNAL_ID 1
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struct mdio_mux_meson_g12a_priv {
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struct udevice *chip;
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phys_addr_t phys;
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};
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static int meson_g12a_ephy_pll_init(struct mdio_mux_meson_g12a_priv *priv)
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{
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/* Fire up the PHY PLL */
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writel(0x29c0040a, priv->phys + ETH_PLL_CTL0);
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writel(0x927e0000, priv->phys + ETH_PLL_CTL1);
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writel(0xac5f49e5, priv->phys + ETH_PLL_CTL2);
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writel(0x00000000, priv->phys + ETH_PLL_CTL3);
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writel(0x00000000, priv->phys + ETH_PLL_CTL4);
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writel(0x20200000, priv->phys + ETH_PLL_CTL5);
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writel(0x0000c002, priv->phys + ETH_PLL_CTL6);
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writel(0x00000023, priv->phys + ETH_PLL_CTL7);
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writel(0x39c0040a, priv->phys + ETH_PLL_CTL0);
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writel(0x19c0040a, priv->phys + ETH_PLL_CTL0);
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return 0;
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}
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static int meson_g12a_enable_internal_mdio(struct mdio_mux_meson_g12a_priv *priv)
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{
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/* Initialize ephy control */
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writel(EPHY_G12A_ID, priv->phys + ETH_PHY_CNTL0);
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writel(FIELD_PREP(PHY_CNTL1_ST_MODE, 3) |
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FIELD_PREP(PHY_CNTL1_ST_PHYADD, EPHY_DFLT_ADD) |
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FIELD_PREP(PHY_CNTL1_MII_MODE, EPHY_MODE_RMII) |
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PHY_CNTL1_CLK_EN |
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PHY_CNTL1_CLKFREQ |
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PHY_CNTL1_PHY_ENB,
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priv->phys + ETH_PHY_CNTL1);
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writel(PHY_CNTL2_USE_INTERNAL |
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PHY_CNTL2_SMI_SRC_MAC |
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PHY_CNTL2_RX_CLK_EPHY,
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priv->phys + ETH_PHY_CNTL2);
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return 0;
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}
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static int meson_g12a_enable_external_mdio(struct mdio_mux_meson_g12a_priv *priv)
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{
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/* Reset the mdio bus mux */
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writel(0x0, priv->phys + ETH_PHY_CNTL2);
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return 0;
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}
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static int mdio_mux_meson_g12a_select(struct udevice *mux, int cur, int sel)
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{
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struct mdio_mux_meson_g12a_priv *priv = dev_get_priv(mux);
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debug("%s: %x -> %x\n", __func__, (u32)cur, (u32)sel);
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/* if last selection didn't change we're good to go */
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if (cur == sel)
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return 0;
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switch (sel) {
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case MESON_G12A_MDIO_EXTERNAL_ID:
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return meson_g12a_enable_external_mdio(priv);
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case MESON_G12A_MDIO_INTERNAL_ID:
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return meson_g12a_enable_internal_mdio(priv);
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct mdio_mux_ops mdio_mux_meson_g12a_ops = {
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.select = mdio_mux_meson_g12a_select,
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};
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static int mdio_mux_meson_g12a_probe(struct udevice *dev)
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{
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struct mdio_mux_meson_g12a_priv *priv = dev_get_priv(dev);
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priv->phys = dev_read_addr(dev);
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meson_g12a_ephy_pll_init(priv);
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return 0;
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}
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static const struct udevice_id mdio_mux_meson_g12a_ids[] = {
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{ .compatible = "amlogic,g12a-mdio-mux" },
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{ }
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};
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U_BOOT_DRIVER(mdio_mux_meson_g12a) = {
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.name = "mdio_mux_meson_g12a",
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.id = UCLASS_MDIO_MUX,
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.of_match = mdio_mux_meson_g12a_ids,
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.probe = mdio_mux_meson_g12a_probe,
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.ops = &mdio_mux_meson_g12a_ops,
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.priv_auto = sizeof(struct mdio_mux_meson_g12a_priv),
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};
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