230 lines
5.8 KiB
C
230 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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* Copyright 2019 Google Inc
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <spl.h>
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#include <acpi/acpigen.h>
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#include <acpi/acpi_device.h>
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#include <asm/lpss.h>
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#include <dm/acpi.h>
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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#include "designware_i2c.h"
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enum {
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VANILLA = 0, /* standard I2C with no tweaks */
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INTEL_APL, /* Apollo Lake I2C */
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};
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/* BayTrail HCNT/LCNT/SDA hold time */
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static struct dw_scl_sda_cfg byt_config = {
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.ss_hcnt = 0x200,
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.fs_hcnt = 0x55,
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.ss_lcnt = 0x200,
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.fs_lcnt = 0x99,
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.sda_hold = 0x6,
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};
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/* Have a weak function for now - possibly should be a new uclass */
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__weak void lpss_reset_release(void *regs);
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static int designware_i2c_pci_of_to_plat(struct udevice *dev)
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{
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struct dw_i2c *priv = dev_get_priv(dev);
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if (spl_phase() < PHASE_SPL) {
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u32 base;
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int ret;
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ret = dev_read_u32(dev, "early-regs", &base);
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if (ret)
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return log_msg_ret("early-regs", ret);
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/* Set i2c base address */
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dm_pci_write_config32(dev, PCI_BASE_ADDRESS_0, base);
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/* Enable memory access and bus master */
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dm_pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER);
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}
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if (spl_phase() < PHASE_BOARD_F) {
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/* Handle early, fixed mapping into a different address space */
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priv->regs = (struct i2c_regs *)dm_pci_read_bar32(dev, 0);
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} else {
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priv->regs = (struct i2c_regs *)
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dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
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}
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if (!priv->regs)
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return -EINVAL;
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/* Save base address from PCI BAR */
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if (IS_ENABLED(CONFIG_INTEL_BAYTRAIL))
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/* Use BayTrail specific timing values */
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priv->scl_sda_cfg = &byt_config;
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if (dev_get_driver_data(dev) == INTEL_APL)
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priv->has_spk_cnt = true;
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return designware_i2c_of_to_plat(dev);
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}
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static int designware_i2c_pci_probe(struct udevice *dev)
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{
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struct dw_i2c *priv = dev_get_priv(dev);
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if (dev_get_driver_data(dev) == INTEL_APL) {
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/* Ensure controller is in D0 state */
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lpss_set_power_state(dev, STATE_D0);
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lpss_reset_release(priv->regs);
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}
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return designware_i2c_probe(dev);
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}
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static int designware_i2c_pci_bind(struct udevice *dev)
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{
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char name[20];
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if (dev_has_ofnode(dev))
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return 0;
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sprintf(name, "i2c_designware#%u", dev_seq(dev));
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device_set_name(dev, name);
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return 0;
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}
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/*
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* Write ACPI object to describe speed configuration.
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*
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* ACPI Object: Name ("xxxx", Package () { scl_lcnt, scl_hcnt, sda_hold }
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*
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* SSCN: I2C_SPEED_STANDARD
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* FMCN: I2C_SPEED_FAST
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* FPCN: I2C_SPEED_FAST_PLUS
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* HSCN: I2C_SPEED_HIGH
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*/
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static void dw_i2c_acpi_write_speed_config(struct acpi_ctx *ctx,
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struct dw_i2c_speed_config *config)
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{
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switch (config->speed_mode) {
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case IC_SPEED_MODE_HIGH:
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acpigen_write_name(ctx, "HSCN");
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break;
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case IC_SPEED_MODE_FAST_PLUS:
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acpigen_write_name(ctx, "FPCN");
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break;
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case IC_SPEED_MODE_FAST:
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acpigen_write_name(ctx, "FMCN");
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break;
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case IC_SPEED_MODE_STANDARD:
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default:
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acpigen_write_name(ctx, "SSCN");
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}
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/* Package () { scl_lcnt, scl_hcnt, sda_hold } */
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acpigen_write_package(ctx, 3);
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acpigen_write_word(ctx, config->scl_hcnt);
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acpigen_write_word(ctx, config->scl_lcnt);
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acpigen_write_dword(ctx, config->sda_hold);
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acpigen_pop_len(ctx);
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}
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/*
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* Generate I2C timing information into the SSDT for the OS driver to consume,
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* optionally applying override values provided by the caller.
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*/
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static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev,
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struct acpi_ctx *ctx)
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{
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struct dw_i2c_speed_config config;
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char path[ACPI_PATH_MAX];
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u32 speeds[4];
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uint speed;
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int size;
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int ret;
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/* If no device-tree node, ignore this since we assume it isn't used */
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if (!dev_has_ofnode(dev))
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return 0;
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ret = acpi_device_path(dev, path, sizeof(path));
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if (ret)
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return log_msg_ret("path", ret);
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size = dev_read_size(dev, "i2c,speeds");
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if (size < 0)
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return log_msg_ret("i2c,speeds", -EINVAL);
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size /= sizeof(u32);
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if (size > ARRAY_SIZE(speeds))
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return log_msg_ret("array", -E2BIG);
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ret = dev_read_u32_array(dev, "i2c,speeds", speeds, size);
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if (ret)
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return log_msg_ret("read", -E2BIG);
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speed = dev_read_u32_default(dev, "clock-frequency", 100000);
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acpigen_write_scope(ctx, path);
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ret = dw_i2c_gen_speed_config(dev, speed, &config);
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if (ret)
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return log_msg_ret("config", ret);
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dw_i2c_acpi_write_speed_config(ctx, &config);
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acpigen_pop_len(ctx);
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return 0;
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}
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struct acpi_ops dw_i2c_acpi_ops = {
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.fill_ssdt = dw_i2c_acpi_fill_ssdt,
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};
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static const struct udevice_id designware_i2c_pci_ids[] = {
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{ .compatible = "snps,designware-i2c-pci" },
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{ .compatible = "intel,apl-i2c", .data = INTEL_APL },
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{ }
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};
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DM_DRIVER_ALIAS(i2c_designware_pci, intel_apl_i2c)
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U_BOOT_DRIVER(i2c_designware_pci) = {
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.name = "i2c_designware_pci",
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.id = UCLASS_I2C,
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.of_match = designware_i2c_pci_ids,
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.bind = designware_i2c_pci_bind,
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.of_to_plat = designware_i2c_pci_of_to_plat,
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.probe = designware_i2c_pci_probe,
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.priv_auto = sizeof(struct dw_i2c),
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.remove = designware_i2c_remove,
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.flags = DM_FLAG_OS_PREPARE,
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.ops = &designware_i2c_ops,
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ACPI_OPS_PTR(&dw_i2c_acpi_ops)
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};
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static struct pci_device_id designware_pci_supported[] = {
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/* Intel BayTrail has 7 I2C controller located on the PCI bus */
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{ PCI_VDEVICE(INTEL, 0x0f41) },
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{ PCI_VDEVICE(INTEL, 0x0f42) },
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{ PCI_VDEVICE(INTEL, 0x0f43) },
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{ PCI_VDEVICE(INTEL, 0x0f44) },
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{ PCI_VDEVICE(INTEL, 0x0f45) },
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{ PCI_VDEVICE(INTEL, 0x0f46) },
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{ PCI_VDEVICE(INTEL, 0x0f47) },
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{ PCI_VDEVICE(INTEL, 0x5aac), .driver_data = INTEL_APL },
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{ PCI_VDEVICE(INTEL, 0x5aae), .driver_data = INTEL_APL },
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{ PCI_VDEVICE(INTEL, 0x5ab0), .driver_data = INTEL_APL },
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{ PCI_VDEVICE(INTEL, 0x5ab2), .driver_data = INTEL_APL },
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{ PCI_VDEVICE(INTEL, 0x5ab4), .driver_data = INTEL_APL },
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{ PCI_VDEVICE(INTEL, 0x5ab6), .driver_data = INTEL_APL },
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{},
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};
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U_BOOT_PCI_DEVICE(i2c_designware_pci, designware_pci_supported);
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