243 lines
6.0 KiB
C
243 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* (C) Copyright 2011
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* eInfochips Ltd. <www.einfochips.com>
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* Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
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*
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* (C) Copyright 2010
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* Marvell Semiconductor <www.marvell.com>
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*/
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#include <dm.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <linux/bitfield.h>
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#include <linux/compat.h>
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#include <dt-bindings/gpio/gpio.h>
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/* Returns the bit value to write or read based on the offset */
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#define GPIO_BIT(x) BIT_ULL((x) & 0x3f)
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#define GPIO_RX_DAT 0x00
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#define GPIO_TX_SET 0x08
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#define GPIO_TX_CLR 0x10
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#define GPIO_CONST 0x90 /* OcteonTX only */
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/* Offset to register-set for 2nd GPIOs (> 63), OcteonTX only */
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#define GPIO1_OFFSET 0x1400
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/* GPIO_CONST register bits */
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#define GPIO_CONST_GPIOS_MASK GENMASK_ULL(7, 0)
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/* GPIO_BIT_CFG register bits */
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#define GPIO_BIT_CFG_TX_OE BIT_ULL(0)
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#define GPIO_BIT_CFG_PIN_XOR BIT_ULL(1)
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#define GPIO_BIT_CFG_INT_EN BIT_ULL(2)
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#define GPIO_BIT_CFG_PIN_SEL_MASK GENMASK_ULL(26, 16)
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enum {
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PROBE_PCI = 0, /* PCI based probing */
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PROBE_DT, /* DT based probing */
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};
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struct octeon_gpio_data {
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int probe;
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u32 reg_offs;
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u32 gpio_bit_cfg_offs;
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};
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struct octeon_gpio {
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void __iomem *base;
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const struct octeon_gpio_data *data;
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};
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/* Returns the offset to the output register based on the offset and value */
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static u32 gpio_tx_reg(int offset, int value)
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{
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u32 ret;
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ret = value ? GPIO_TX_SET : GPIO_TX_CLR;
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if (offset > 63)
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ret += GPIO1_OFFSET;
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return ret;
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}
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/* Returns the offset to the input data register based on the offset */
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static u32 gpio_rx_dat_reg(int offset)
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{
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u32 ret;
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ret = GPIO_RX_DAT;
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if (offset > 63)
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ret += GPIO1_OFFSET;
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return ret;
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}
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static int octeon_gpio_dir_input(struct udevice *dev, unsigned int offset)
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{
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struct octeon_gpio *gpio = dev_get_priv(dev);
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debug("%s(%s, %u)\n", __func__, dev->name, offset);
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clrbits_64(gpio->base + gpio->data->gpio_bit_cfg_offs + 8 * offset,
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GPIO_BIT_CFG_TX_OE | GPIO_BIT_CFG_PIN_XOR |
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GPIO_BIT_CFG_INT_EN | GPIO_BIT_CFG_PIN_SEL_MASK);
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return 0;
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}
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static int octeon_gpio_dir_output(struct udevice *dev, unsigned int offset,
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int value)
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{
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struct octeon_gpio *gpio = dev_get_priv(dev);
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debug("%s(%s, %u, %d)\n", __func__, dev->name, offset, value);
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writeq(GPIO_BIT(offset), gpio->base + gpio->data->reg_offs +
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gpio_tx_reg(offset, value));
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clrsetbits_64(gpio->base + gpio->data->gpio_bit_cfg_offs + 8 * offset,
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GPIO_BIT_CFG_PIN_SEL_MASK | GPIO_BIT_CFG_INT_EN,
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GPIO_BIT_CFG_TX_OE);
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return 0;
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}
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static int octeon_gpio_get_value(struct udevice *dev, unsigned int offset)
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{
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struct octeon_gpio *gpio = dev_get_priv(dev);
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u64 reg = readq(gpio->base + gpio->data->reg_offs +
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gpio_rx_dat_reg(offset));
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debug("%s(%s, %u): value: %d\n", __func__, dev->name, offset,
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!!(reg & GPIO_BIT(offset)));
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return !!(reg & GPIO_BIT(offset));
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}
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static int octeon_gpio_set_value(struct udevice *dev,
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unsigned int offset, int value)
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{
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struct octeon_gpio *gpio = dev_get_priv(dev);
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debug("%s(%s, %u, %d)\n", __func__, dev->name, offset, value);
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writeq(GPIO_BIT(offset), gpio->base + gpio->data->reg_offs +
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gpio_tx_reg(offset, value));
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return 0;
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}
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static int octeon_gpio_get_function(struct udevice *dev, unsigned int offset)
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{
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struct octeon_gpio *gpio = dev_get_priv(dev);
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u64 val = readq(gpio->base + gpio->data->gpio_bit_cfg_offs +
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8 * offset);
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int pin_sel;
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debug("%s(%s, %u): GPIO_BIT_CFG: 0x%llx\n", __func__, dev->name,
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offset, val);
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pin_sel = FIELD_GET(GPIO_BIT_CFG_PIN_SEL_MASK, val);
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if (pin_sel)
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return GPIOF_FUNC;
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else if (val & GPIO_BIT_CFG_TX_OE)
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return GPIOF_OUTPUT;
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else
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return GPIOF_INPUT;
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}
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static int octeon_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
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struct ofnode_phandle_args *args)
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{
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if (args->args_count < 1)
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return -EINVAL;
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desc->offset = args->args[0];
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desc->flags = 0;
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if (args->args_count > 1) {
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if (args->args[1] & GPIO_ACTIVE_LOW)
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desc->flags |= GPIOD_ACTIVE_LOW;
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/* In the future add tri-state flag support */
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}
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return 0;
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}
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static const struct dm_gpio_ops octeon_gpio_ops = {
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.direction_input = octeon_gpio_dir_input,
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.direction_output = octeon_gpio_dir_output,
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.get_value = octeon_gpio_get_value,
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.set_value = octeon_gpio_set_value,
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.get_function = octeon_gpio_get_function,
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.xlate = octeon_gpio_xlate,
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};
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static int octeon_gpio_probe(struct udevice *dev)
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{
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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struct octeon_gpio *priv = dev_get_priv(dev);
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char *end;
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priv->data = (const struct octeon_gpio_data *)dev_get_driver_data(dev);
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if (priv->data->probe == PROBE_PCI) {
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priv->base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
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PCI_REGION_MEM);
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uc_priv->gpio_count = readq(priv->base +
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priv->data->reg_offs + GPIO_CONST) &
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GPIO_CONST_GPIOS_MASK;
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} else {
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priv->base = dev_remap_addr(dev);
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uc_priv->gpio_count = ofnode_read_u32_default(dev_ofnode(dev),
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"nr-gpios", 32);
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}
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if (!priv->base) {
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debug("%s(%s): Could not get base address\n",
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__func__, dev->name);
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return -ENODEV;
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}
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uc_priv->bank_name = strdup(dev->name);
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end = strchr(uc_priv->bank_name, '@');
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end[0] = 'A' + dev_seq(dev);
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end[1] = '\0';
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debug("%s(%s): base address: %p, pin count: %d\n",
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__func__, dev->name, priv->base, uc_priv->gpio_count);
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return 0;
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}
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static const struct octeon_gpio_data gpio_octeon_data = {
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.probe = PROBE_DT,
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.reg_offs = 0x80,
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.gpio_bit_cfg_offs = 0x100,
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};
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static const struct octeon_gpio_data gpio_octeontx_data = {
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.probe = PROBE_PCI,
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.reg_offs = 0x00,
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.gpio_bit_cfg_offs = 0x400,
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};
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static const struct udevice_id octeon_gpio_ids[] = {
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{ .compatible = "cavium,thunder-8890-gpio",
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.data = (ulong)&gpio_octeontx_data },
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{ .compatible = "cavium,octeon-7890-gpio",
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.data = (ulong)&gpio_octeon_data },
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{ }
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};
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U_BOOT_DRIVER(octeon_gpio) = {
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.name = "octeon_gpio",
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.id = UCLASS_GPIO,
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.of_match = of_match_ptr(octeon_gpio_ids),
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.probe = octeon_gpio_probe,
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.priv_auto = sizeof(struct octeon_gpio),
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.ops = &octeon_gpio_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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