291 lines
7.1 KiB
C
291 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Broadcom
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/devres.h>
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#include <dm/pinctrl.h>
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/*
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* There are five GPIO bank register. Each bank can configure max of 32 gpios.
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* BANK0 - gpios 0 to 31
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* BANK1 - gpios 32 to 63
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* BANK2 - gpios 64 to 95
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* BANK3 - gpios 96 to 127
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* BANK4 - gpios 128 to 150
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*
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* Offset difference between consecutive bank register is 0x200
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*/
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#define NGPIO_PER_BANK 32
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#define GPIO_BANK_SIZE 0x200
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#define GPIO_BANK(pin) ((pin) / NGPIO_PER_BANK)
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#define GPIO_SHIFT(pin) ((pin) % NGPIO_PER_BANK)
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#define GPIO_REG(pin, reg) (GPIO_BANK_SIZE * GPIO_BANK(pin) + (reg))
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/* device register offset */
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#define DATA_IN_OFFSET 0x00
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#define DATA_OUT_OFFSET 0x04
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#define OUT_EN_OFFSET 0x08
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/**
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* struct iproc_gpio_pctrl_map - gpio and pinctrl mapping
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* @gpio_pin: start of gpio number in gpio-ranges
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* @pctrl_pin: start of pinctrl number in gpio-ranges
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* @npins: total number of pins in gpio-ranges
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* @node: list node
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*/
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struct iproc_gpio_pctrl_map {
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u32 gpio_pin;
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u32 pctrl_pin;
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u32 npins;
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struct list_head node;
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};
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/**
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* struct iproc_gpio_pctrl_map - gpio device instance
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* @pinctrl_dev:pointer to pinctrl device
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* @gpiomap: list node having mapping between gpio and pinctrl
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* @base: I/O register base address of gpio device
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* @name: gpio device name, ex GPIO0, GPIO1
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* @ngpios: total number of gpios
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*/
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struct iproc_gpio_plat {
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struct udevice *pinctrl_dev;
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struct list_head gpiomap;
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void __iomem *base;
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char *name;
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u32 ngpios;
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};
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/**
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* iproc_gpio_set_bit - set or clear one bit in an iproc GPIO register.
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*
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* The bit relates to a GPIO pin.
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*
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* @plat: iproc GPIO device
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* @reg: register offset
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* @gpio: GPIO pin
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* @set: set or clear
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*/
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static inline void iproc_gpio_set_bit(struct iproc_gpio_plat *plat,
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u32 reg, u32 gpio, bool set)
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{
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u32 offset = GPIO_REG(gpio, reg);
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u32 shift = GPIO_SHIFT(gpio);
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clrsetbits_le32(plat->base + offset, BIT(shift),
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(set ? BIT(shift) : 0));
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}
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static inline bool iproc_gpio_get_bit(struct iproc_gpio_plat *plat,
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u32 reg, u32 gpio)
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{
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u32 offset = GPIO_REG(gpio, reg);
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u32 shift = GPIO_SHIFT(gpio);
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return readl(plat->base + offset) & BIT(shift);
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}
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/**
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* iproc_get_gpio_pctrl_mapping() - get associated pinctrl pin from gpio pin
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*
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* @plat: iproc GPIO device
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* @gpio: GPIO pin
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*/
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static u32 iproc_get_pctrl_from_gpio(struct iproc_gpio_plat *plat, u32 gpio)
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{
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struct iproc_gpio_pctrl_map *range = NULL;
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struct list_head *pos, *tmp;
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u32 ret = 0;
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list_for_each_safe(pos, tmp, &plat->gpiomap) {
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range = list_entry(pos, struct iproc_gpio_pctrl_map, node);
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if (gpio == range->gpio_pin ||
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gpio < (range->gpio_pin + range->npins)) {
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ret = range->pctrl_pin + (gpio - range->gpio_pin);
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break;
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}
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}
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return ret;
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}
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/**
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* iproc_get_gpio_pctrl_mapping() - get mapping between gpio and pinctrl
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*
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* Read dt node "gpio-ranges" to get gpio and pinctrl mapping and store
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* in private data structure to use it later while enabling gpio.
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*
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* @dev: pointer to GPIO device
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* @return 0 on success and -ENOMEM on failure
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*/
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static int iproc_get_gpio_pctrl_mapping(struct udevice *dev)
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{
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struct iproc_gpio_plat *plat = dev_get_plat(dev);
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struct iproc_gpio_pctrl_map *range = NULL;
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struct ofnode_phandle_args args;
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int index = 0, ret;
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for (;; index++) {
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ret = dev_read_phandle_with_args(dev, "gpio-ranges",
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NULL, 3, index, &args);
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if (ret)
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break;
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range = devm_kzalloc(dev, sizeof(*range), GFP_KERNEL);
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if (!range)
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return -ENOMEM;
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range->gpio_pin = args.args[0];
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range->pctrl_pin = args.args[1];
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range->npins = args.args[2];
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list_add_tail(&range->node, &plat->gpiomap);
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}
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return 0;
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}
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static int iproc_gpio_request(struct udevice *dev, u32 gpio, const char *label)
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{
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struct iproc_gpio_plat *plat = dev_get_plat(dev);
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u32 pctrl;
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/* nothing to do if there is no corresponding pinctrl device */
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if (!plat->pinctrl_dev)
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return 0;
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pctrl = iproc_get_pctrl_from_gpio(plat, gpio);
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return pinctrl_request(plat->pinctrl_dev, pctrl, 0);
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}
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static int iproc_gpio_direction_input(struct udevice *dev, u32 gpio)
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{
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struct iproc_gpio_plat *plat = dev_get_plat(dev);
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iproc_gpio_set_bit(plat, OUT_EN_OFFSET, gpio, false);
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dev_dbg(dev, "gpio:%u set input\n", gpio);
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return 0;
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}
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static int iproc_gpio_direction_output(struct udevice *dev, u32 gpio, int value)
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{
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struct iproc_gpio_plat *plat = dev_get_plat(dev);
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iproc_gpio_set_bit(plat, OUT_EN_OFFSET, gpio, true);
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iproc_gpio_set_bit(plat, DATA_OUT_OFFSET, gpio, value);
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dev_dbg(dev, "gpio:%u set output, value:%d\n", gpio, value);
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return 0;
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}
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static int iproc_gpio_get_value(struct udevice *dev, u32 gpio)
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{
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struct iproc_gpio_plat *plat = dev_get_plat(dev);
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int value;
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value = iproc_gpio_get_bit(plat, DATA_IN_OFFSET, gpio);
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dev_dbg(dev, "gpio:%u get, value:%d\n", gpio, value);
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return value;
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}
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static int iproc_gpio_set_value(struct udevice *dev, u32 gpio, int value)
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{
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struct iproc_gpio_plat *plat = dev_get_plat(dev);
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if (iproc_gpio_get_bit(plat, OUT_EN_OFFSET, gpio))
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iproc_gpio_set_bit(plat, DATA_OUT_OFFSET, gpio, value);
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dev_dbg(dev, "gpio:%u set, value:%d\n", gpio, value);
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return 0;
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}
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static int iproc_gpio_get_function(struct udevice *dev, u32 gpio)
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{
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struct iproc_gpio_plat *plat = dev_get_plat(dev);
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if (iproc_gpio_get_bit(plat, OUT_EN_OFFSET, gpio))
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return GPIOF_OUTPUT;
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else
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return GPIOF_INPUT;
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}
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static int iproc_gpio_of_to_plat(struct udevice *dev)
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{
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struct iproc_gpio_plat *plat = dev_get_plat(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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int ret;
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char name[10];
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plat->base = dev_read_addr_ptr(dev);
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if (!plat->base) {
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debug("%s: Failed to get base address\n", __func__);
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return -EINVAL;
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}
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ret = dev_read_u32(dev, "ngpios", &plat->ngpios);
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if (ret < 0) {
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dev_err(dev, "%s: Failed to get ngpios\n", __func__);
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return ret;
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}
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uclass_get_device_by_phandle(UCLASS_PINCTRL, dev, "gpio-ranges",
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&plat->pinctrl_dev);
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if (ret < 0) {
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dev_err(dev, "%s: Failed to get pinctrl phandle\n", __func__);
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return ret;
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}
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INIT_LIST_HEAD(&plat->gpiomap);
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ret = iproc_get_gpio_pctrl_mapping(dev);
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if (ret < 0) {
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dev_err(dev, "%s: Failed to get gpio to pctrl map ret(%d)\n",
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__func__, ret);
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return ret;
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}
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snprintf(name, sizeof(name), "GPIO%d", dev_seq(dev));
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plat->name = strdup(name);
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if (!plat->name)
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return -ENOMEM;
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uc_priv->gpio_count = plat->ngpios;
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uc_priv->bank_name = plat->name;
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dev_info(dev, ":bank name(%s) base %p, #gpios %d\n",
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plat->name, plat->base, plat->ngpios);
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return 0;
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}
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static const struct dm_gpio_ops iproc_gpio_ops = {
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.request = iproc_gpio_request,
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.direction_input = iproc_gpio_direction_input,
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.direction_output = iproc_gpio_direction_output,
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.get_value = iproc_gpio_get_value,
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.set_value = iproc_gpio_set_value,
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.get_function = iproc_gpio_get_function,
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};
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static const struct udevice_id iproc_gpio_ids[] = {
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{ .compatible = "brcm,iproc-gpio" },
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{ }
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};
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U_BOOT_DRIVER(iproc_gpio) = {
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.name = "iproc_gpio",
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.id = UCLASS_GPIO,
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.of_match = iproc_gpio_ids,
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.ops = &iproc_gpio_ops,
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.of_to_plat = iproc_gpio_of_to_plat,
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.plat_auto = sizeof(struct iproc_gpio_plat),
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};
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