155 lines
3.4 KiB
C
155 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* OMAP clock controller support
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*
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <clk-uclass.h>
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#include <asm/arch-am33xx/clock.h>
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struct clk_ti_ctrl_offs {
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fdt_addr_t start;
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fdt_size_t end;
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};
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struct clk_ti_ctrl_priv {
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int offs_num;
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struct clk_ti_ctrl_offs *offs;
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};
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static int clk_ti_ctrl_check_offs(struct clk *clk, fdt_addr_t offs)
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{
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struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
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int i;
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for (i = 0; i < priv->offs_num; i++) {
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if (offs >= priv->offs[i].start && offs <= priv->offs[i].end)
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return 0;
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}
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return -EFAULT;
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}
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static int clk_ti_ctrl_disable(struct clk *clk)
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{
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struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
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u32 *clk_modules[2] = { };
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fdt_addr_t offs;
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int err;
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offs = priv->offs[0].start + clk->id;
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err = clk_ti_ctrl_check_offs(clk, offs);
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if (err) {
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dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
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return err;
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}
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clk_modules[0] = (u32 *)(offs);
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dev_dbg(clk->dev, "disable module @ %p\n", clk_modules[0]);
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do_disable_clocks(NULL, clk_modules, 1);
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return 0;
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}
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static int clk_ti_ctrl_enable(struct clk *clk)
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{
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struct clk_ti_ctrl_priv *priv = dev_get_priv(clk->dev);
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u32 *clk_modules[2] = { };
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fdt_addr_t offs;
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int err;
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offs = priv->offs[0].start + clk->id;
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err = clk_ti_ctrl_check_offs(clk, offs);
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if (err) {
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dev_err(clk->dev, "invalid offset: 0x%lx\n", offs);
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return err;
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}
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clk_modules[0] = (u32 *)(offs);
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dev_dbg(clk->dev, "enable module @ %p\n", clk_modules[0]);
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do_enable_clocks(NULL, clk_modules, 1);
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return 0;
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}
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static ulong clk_ti_ctrl_get_rate(struct clk *clk)
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{
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return 0;
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}
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static int clk_ti_ctrl_of_xlate(struct clk *clk,
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struct ofnode_phandle_args *args)
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{
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if (args->args_count != 2) {
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dev_err(clk->dev, "invaild args_count: %d\n", args->args_count);
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return -EINVAL;
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}
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if (args->args_count)
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clk->id = args->args[0];
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else
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clk->id = 0;
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dev_dbg(clk->dev, "name=%s, id=%ld\n", clk->dev->name, clk->id);
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return 0;
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}
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static int clk_ti_ctrl_of_to_plat(struct udevice *dev)
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{
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struct clk_ti_ctrl_priv *priv = dev_get_priv(dev);
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fdt_size_t fdt_size;
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int i, size;
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size = dev_read_size(dev, "reg");
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if (size < 0) {
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dev_err(dev, "failed to get 'reg' size\n");
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return size;
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}
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priv->offs_num = size / 2 / sizeof(u32);
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dev_dbg(dev, "size=%d, regs_num=%d\n", size, priv->offs_num);
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priv->offs = kmalloc_array(priv->offs_num, sizeof(*priv->offs),
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GFP_KERNEL);
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if (!priv->offs)
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return -ENOMEM;
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for (i = 0; i < priv->offs_num; i++) {
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priv->offs[i].start =
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dev_read_addr_size_index(dev, i, &fdt_size);
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if (priv->offs[i].start == FDT_ADDR_T_NONE) {
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dev_err(dev, "failed to get offset %d\n", i);
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return -EINVAL;
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}
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priv->offs[i].end = priv->offs[i].start + fdt_size;
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dev_dbg(dev, "start=0x%08lx, end=0x%08lx\n",
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priv->offs[i].start, priv->offs[i].end);
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}
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return 0;
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}
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static struct clk_ops clk_ti_ctrl_ops = {
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.of_xlate = clk_ti_ctrl_of_xlate,
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.enable = clk_ti_ctrl_enable,
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.disable = clk_ti_ctrl_disable,
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.get_rate = clk_ti_ctrl_get_rate,
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};
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static const struct udevice_id clk_ti_ctrl_ids[] = {
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{.compatible = "ti,clkctrl"},
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{},
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};
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U_BOOT_DRIVER(clk_ti_ctrl) = {
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.name = "ti_ctrl_clk",
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.id = UCLASS_CLK,
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.of_match = clk_ti_ctrl_ids,
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.of_to_plat = clk_ti_ctrl_of_to_plat,
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.ops = &clk_ti_ctrl_ops,
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.priv_auto = sizeof(struct clk_ti_ctrl_priv),
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};
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