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2f27c9219e
Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
45 lines
1.4 KiB
C
45 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2020 Microchip Technology Inc.
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* Padmarao Begari <padmarao.begari@microchip.com>
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*/
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#ifndef __MICROCHIP_MPFS_CLK_H
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#define __MICROCHIP_MPFS_CLK_H
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#include <linux/clk-provider.h>
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/**
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* mpfs_clk_register_cfgs() - register configuration clocks
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*
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* @base: base address of the mpfs system register.
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* @clk_rate: the mpfs pll clock rate.
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* @parent_name: a pointer to parent clock name.
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* @return zero on success, or a negative error code.
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*/
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int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate,
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const char *parent_name);
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/**
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* mpfs_clk_register_periphs() - register peripheral clocks
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*
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* @base: base address of the mpfs system register.
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* @clk_rate: the mpfs pll clock rate.
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* @parent_name: a pointer to parent clock name.
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* @return zero on success, or a negative error code.
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*/
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int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate,
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const char *parent_name);
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/**
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* divider_get_val() - get the clock divider value
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*
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* @rate: requested clock rate.
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* @parent_rate: parent clock rate.
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* @table: a pointer to clock divider table.
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* @width: width of the divider bit field.
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* @flags: common clock framework flags.
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* @return divider value on success, or a negative error code.
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*/
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int divider_get_val(unsigned long rate, unsigned long parent_rate,
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const struct clk_div_table *table,
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u8 width, unsigned long flags);
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#endif /* __MICROCHIP_MPFS_CLK_H */
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