mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
40b383fa84
Zynq is using Cadence IP where binding is documented in the Linux kernel and there is no reason to use different binding. Synchronize it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
33 lines
1.1 KiB
Plaintext
33 lines
1.1 KiB
Plaintext
Cadence SPI controller Device Tree Bindings
|
|
-------------------------------------------
|
|
|
|
Required properties:
|
|
- compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
|
|
- reg : Physical base address and size of SPI registers map.
|
|
- interrupts : Property with a value describing the interrupt
|
|
number.
|
|
- interrupt-parent : Must be core interrupt controller
|
|
- clock-names : List of input clock names - "ref_clk", "pclk"
|
|
(See clock bindings for details).
|
|
- clocks : Clock phandles (see clock bindings for details).
|
|
- spi-max-frequency : Maximum SPI clocking speed of device in Hz
|
|
|
|
Optional properties:
|
|
- num-cs : Number of chip selects used.
|
|
If a decoder is used, this will be the number of
|
|
chip selects after the decoder.
|
|
- is-decoded-cs : Flag to indicate whether decoder is used or not.
|
|
|
|
Example:
|
|
|
|
spi@e0007000 {
|
|
compatible = "xlnx,zynq-spi-r1p6";
|
|
clock-names = "ref_clk", "pclk";
|
|
clocks = <&clkc 26>, <&clkc 35>;
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <0 49 4>;
|
|
num-cs = <4>;
|
|
is-decoded-cs = <0>;
|
|
reg = <0xe0007000 0x1000>;
|
|
} ;
|