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https://github.com/brain-hackers/u-boot-brain
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88364387c6
This patch adds the cros_ec driver that implements the protocol for communicating with Google's ChromeOS embedded controller. Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Hung-ying Tyan <tyanh@chromium.org> Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
39 lines
1.0 KiB
Plaintext
39 lines
1.0 KiB
Plaintext
Chrome OS CROS_EC Binding
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======================
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The device tree node which describes the operation of the CROS_EC interface
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is as follows:
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Required properties :
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- compatible = "google,cros-ec"
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Optional properties :
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- spi-max-frequency : Sets the maximum frequency (in Hz) for SPI bus
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operation
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- i2c-max-frequency : Sets the maximum frequency (in Hz) for I2C bus
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operation
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- ec-interrupt : Selects the EC interrupt, defined as a GPIO according
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to the platform
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- optimise-flash-write : Boolean property - if present then flash blocks
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containing all 0xff will not be written, since we assume that the EC
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uses that pattern for erased blocks
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The CROS_EC node should appear as a subnode of the interrupt that connects it
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to the EC (e.g. i2c, spi, lpc). The reg property (as usual) will indicate
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the unit address on that bus.
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Example
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=======
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spi@131b0000 {
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cros-ec@0 {
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reg = <0>;
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compatible = "google,cros-ec";
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spi-max-frequency = <5000000>;
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ec-interrupt = <&gpio 174 1>;
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optimise-flash-write;
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status = "disabled";
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};
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};
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