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https://github.com/brain-hackers/u-boot-brain
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674c58c7b7
The term eMMC is used inconsistently within the FSP devicetree bindings (e-mmc and emmc), especially for "emmc-host-max-speed" documentation and code disagree. Change all eMMC instances within the FSP bindings to consistently use "emmc". The term "emmc" is already used a lot within U-Boot, while "e-mmc" is only used in the FSP bindings. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct one typo in the commit message] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
328 lines
9.6 KiB
Plaintext
328 lines
9.6 KiB
Plaintext
* Intel FSP-M configuration
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Several Intel platforms require the execution of the Intel FSP (Firmware
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Support Package) for initialization. The FSP consists of multiple parts, one
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of which is the FSP-M (Memory initialization phase).
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This binding applies to the FSP-M for the Intel Apollo Lake SoC.
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The FSP-M is available on Github [1].
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For detailed information on the FSP-M parameters see the documentation in
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FSP/ApolloLakeFspBinPkg/Docs [2].
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The properties of this binding are all optional. If no properties are set the
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values of the FSP-M are used.
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[1] https://github.com/IntelFsp/FSP
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[2] https://github.com/IntelFsp/FSP/tree/master/ApolloLakeFspBinPkg/Docs
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Optional properties:
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- fspm,training-delay: Time taken to train DDR memory if there is no cached MRC
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data, in seconds. This is used to show a message if possible. For Chromebook
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Coral this is typically 21 seconds. For an APL board with 1GB of RAM, it may
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be only 6 seconds.
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- fspm,serial-debug-port-address: Debug Serial Port Base address
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- fspm,serial-debug-port-type: Debug Serial Port Type
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0: NONE
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1: I/O
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2: MMIO (default)
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- fspm,serial-debug-port-device: Serial Port Debug Device
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0: SOC UART0
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1: SOC UART1
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2: SOC UART2 (default)
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3: External Device
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- fspm,serial-debug-port-stride-size: Debug Serial Port Stride Size
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0: 1
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2: 4 (default)
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- fspm,mrc-fast-boot: Memory Fast Boot
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- fspm,igd: Integrated Graphics Device
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- fspm,igd-dvmt50-pre-alloc: DVMT Pre-Allocated
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0x02: 64 MB (default)
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0x03: 96 MB
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0x04: 128 MB
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0x05: 160 MB
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0x06: 192 MB
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0x07: 224 MB
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0x08: 256 MB
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0x09: 288 MB
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0x0A: 320 MB
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0x0B: 352 MB
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0x0C: 384 MB
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0x0D: 416 MB
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0x0E: 448 MB
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0x0F: 480 MB
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0x10: 512 MB
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- fspm,aperture-size: Aperture Size
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0x1: 128 MB (default)
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0x2: 256 MB
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0x3: 512 MB
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- fspm,gtt-size: GTT Size
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0x1: 2 MB
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0x2: 4 MB
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0x3: 8 MB (default)
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- fspm,primary-video-adaptor: Primary Display
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0x0: AUTO (default)
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0x2: IGD
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0x3: PCI
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- fspm,package: Package
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0x0: SODIMM (default)
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0x1: BGA
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0x2: BGA mirrored (LPDDR3 only)
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0x3: SODIMM/UDIMM with Rank 1 Mirrored (DDR3L)
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- fspm,profile: Profile
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0x01: WIO2_800_7_8_8
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0x02: WIO2_1066_9_10_10
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0x03: LPDDR3_1066_8_10_10
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0x04: LPDDR3_1333_10_12_12
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0x05: LPDDR3_1600_12_15_15
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0x06: LPDDR3_1866_14_17_17
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0x07: LPDDR3_2133_16_20_20
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0x08: LPDDR4_1066_10_10_10
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0x09: LPDDR4_1600_14_15_15
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0x0A: LPDDR4_2133_20_20_20
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0x0B: LPDDR4_2400_24_22_22
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0x0C: LPDDR4_2666_24_24_24
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0x0D: LPDDR4_2933_28_27_27
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0x0E: LPDDR4_3200_28_29_29
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0x0F: DDR3_1066_6_6_6
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0x10: DDR3_1066_7_7_7
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0x11: DDR3_1066_8_8_8
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0x12: DDR3_1333_7_7_7
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0x13: DDR3_1333_8_8_8
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0x14: DDR3_1333_9_9_9
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0x15: DDR3_1333_10_10_10
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0x16: DDR3_1600_8_8_8
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0x17: DDR3_1600_9_9_9
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0x18: DDR3_1600_10_10_10
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0x19: DDR3_1600_11_11_11 (default)
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0x1A: DDR3_1866_10_10_10
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0x1B: DDR3_1866_11_11_11
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0x1C: DDR3_1866_12_12_12
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0x1D: DDR3_1866_13_13_13
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0x1E: DDR3_2133_11_11_11
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0x1F: DDR3_2133_12_12_12
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0x20: DDR3_2133_13_13_13
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0x21: DDR3_2133_14_14_14
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0x22: DDR4_1333_10_10_10
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0x23: DDR4_1600_10_10_10
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0x24: DDR4_1600_11_11_11
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0x25: DDR4_1600_12_12_12
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0x26: DDR4_1866_12_12_12
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0x27: DDR4_1866_13_13_13
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0x28: DDR4_1866_14_14_14
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0x29: DDR4_2133_14_14_14
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0x2A: DDR4_2133_15_15_15
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0x2B: DDR4_2133_16_16_16
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0x2C: DDR4_2400_15_15_15
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0x2D: DDR4_2400_16_16_16
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0x2E: DDR4_2400_17_17_17
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0x2F: DDR4_2400_18_18_18
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- fspm,memory-down: Memory Down
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0x0: No (default)
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0x1: Yes
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0x2: 1MD+SODIMM (for DDR3L only) ACRD
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0x3: 1x32 LPDDR4
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- fspm,ddr3l-page-size: DDR3LPageSize
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0x1: 1KB (default)
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0x2: 2KB
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- fspm,ddr3-lasr: DDR3LASR
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- fspm,scrambler-support: ScramblerSupport
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- fspm,interleaved-mode: InterleavedMode
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- fspm,channel-hash-mask: ChannelHashMask
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- fspm,fspm,slice-hash-mask: SliceHashMask
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- fspm,channels-slices-enable: ChannelsSlices
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- fspm,min-ref-rate2x-enable: MinRefRate2x
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- fspm,dual-rank-support-enable: DualRankSupport
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- fspm,rmt-mode: RmtMode
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- fspm,memory-size-limit: MemorySizeLimit
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- fspm,low-memory-max-value: LowMemoryMaxValue
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- fspm,high-memory-max-value: HighMemoryMaxValue
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- fspm,disable-fast-boot: FastBoot
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- fspm,dimm0-spd-address: DIMM0 SPD Address
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- fspm,dimm1-spd-address: DIMM1 SPD Address
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- fspm,chX-rank-enable: Must be set to enable rank (X = 0-3)
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- fspm,chX-device-width: DRAM device width per DRAM channel (X = 0-3)
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0: x8
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1: x16
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2: x32
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3: x64
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- fspm,chX-dram-density: Must specify the DRAM device density (X = 0-3)
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0: 4Gb
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1: 6Gb
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2: 8Gb
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3: 12Gb
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4: 16Gb
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5: 2Gb
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- fspm,chX-option: Channel options (X = 0-3)
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- fspm,chX-odt-config: Channel Odt Config (X = 0-3)
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- fspm,chX-mode2-n: Force 2N Mode (X = 0-3)
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0x0: Auto
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0x1: Force 2N CMD Timing Mode
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- fspm,chX-odt-levels: Channel Odt Levels (X = 0-3)
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0: ODT Connected to SoC
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1: ODT held high
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- fspm,rmt-check-run: RmtCheckRun
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- fspm,rmt-margin-check-scale-high-threshold: RmtMarginCheckScaleHighThreshold
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- fspm,ch-bit-swizzling: Bit_swizzling
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- fspm,msg-level-mask: MsgLevelMask
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- fspm,pre-mem-gpio-table-pin-num: PreMem GPIO Pin Number for each table
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- fspm,pre-mem-gpio-table-ptr: PreMem GPIO Table Pointer
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- fspm,pre-mem-gpio-table-entry-num: PreMem GPIO Table Entry Number
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- fspm,enhance-port8xh-decoding: Enhance the port 8xh decoding
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- fspm,spd-write-enable: SPD Data Write
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- fspm,mrc-data-saving: MRC Training Data Saving
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- fspm,oem-loading-base: OEM File Loading Address
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- fspm,oem-file-name: OEM File Name to Load
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- fspm,mrc-boot-data-ptr:
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- fspm,emmc-trace-len: eMMC Trace Length
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0x0: Long
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0x1: Short
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- fspm,skip-cse-rbp: Skip CSE RBP to support zero sized IBB
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- fspm,npk-en: Npk Enable
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0: Disable
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1: Enable
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2: Debugger
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3: Auto (default)
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- fspm,fw-trace-en: FW Trace Enable
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- fspm,fw-trace-destination: FW Trace Destination
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1: NPK_TRACE_TO_MEMORY
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2: NPK_TRACE_TO_DCI
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3: NPK_TRACE_TO_BSSB
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4: NPK_TRACE_TO_PTI (default)
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- fspm,recover-dump: NPK Recovery Dump
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- fspm,msc0-wrap: Memory Region 0 Buffer WrapAround
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0: n0-warp
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1: n1-warp (default)
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- fspm,msc1-wrap: Memory Region 1 Buffer WrapAround
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0: n0-warp
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1: n1-warp (default)
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- fspm,msc0-size: Memory Region 0 Buffer Size
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0: 0MB (default)
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1: 1MB
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2: 8MB
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3: 64MB
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4: 128MB
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5: 256MB
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6: 512MB
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7: 1GB
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- fspm,msc1-size: Memory Region 1 Buffer Size
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0: 0MB (default)
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1: 1MB
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2: 8MB
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3: 64MB
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4: 128MB
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5: 256MB
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6: 512MB
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7: 1GB
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- fspm,pti-mode: PTI Mode
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0: 0ff
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1: x4 (default)
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2: x8
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3: x12
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4: x16
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- fspm,pti-training: PTI Training
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0: off (default)
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1-6: 1-6
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- fspm,pti-speed:
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0: full
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1: half
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2: quarter (default)
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- fspm,punit-mlvl: Punit Message Level
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0:
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1: (default)
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2-4: 2-4
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- fspm,pmc-mlvl: PMC Message Level
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0:
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1: (default)
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2-4: 2-4
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- fspm,sw-trace-en: SW Trace Enable
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- fspm,periodic-retraining-disable: Periodic Retraining Disable
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- fspm,enable-reset-system: Enable Reset System
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- fspm,enable-s3-heci2: Enable HECI2 in S3 resume path
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- fspm,variable-nvs-buffer-ptr:
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- fspm,start-timer-ticker-of-pfet-assert: PCIE SLOT Power Enable Assert Time - PFET
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- fspm,rt-en: Real Time Enabling
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- fspm,skip-pcie-power-sequence: Skip Pcie Power Sequence
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Example:
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&host_bridge {
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fspm,package = <PACKAGE_BGA>;
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fspm,profile = <PROFILE_LPDDR4_2400_24_22_22>;
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fspm,memory-down = <MEMORY_DOWN_YES>;
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fspm,scrambler-support = <1>;
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fspm,interleaved-mode = <INTERLEAVED_MODE_ENABLE>;
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fspm,channel-hash-mask = <0x36>;
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fspm,slice-hash-mask = <0x9>;
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fspm,low-memory-max-value = <2048>;
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fspm,ch0-rank-enable = <1>;
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fspm,ch0-device-width = <CHX_DEVICE_WIDTH_X16>;
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fspm,ch0-dram-density = <CHX_DEVICE_DENSITY_8GB>;
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fspm,ch0-option = <(CHX_OPTION_RANK_INTERLEAVING |
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CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
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fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
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fspm,ch1-rank-enable = <1>;
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fspm,ch1-device-width = <CHX_DEVICE_WIDTH_X16>;
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fspm,ch1-dram-density = <CHX_DEVICE_DENSITY_8GB>;
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fspm,ch1-option = <(CHX_OPTION_RANK_INTERLEAVING |
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CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
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fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
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fspm,ch2-rank-enable = <1>;
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fspm,ch2-device-width = <CHX_DEVICE_WIDTH_X16>;
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fspm,ch2-dram-density = <CHX_DEVICE_DENSITY_8GB>;
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fspm,ch2-option = <(CHX_OPTION_RANK_INTERLEAVING |
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CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
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fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
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fspm,ch3-rank-enable = <1>;
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fspm,ch3-device-width = <CHX_DEVICE_WIDTH_X16>;
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fspm,ch3-dram-density = <CHX_DEVICE_DENSITY_8GB>;
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fspm,ch3-option = <(CHX_OPTION_RANK_INTERLEAVING |
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CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE)>;
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fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
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fspm,fspm,skip-cse-rbp = <1>;
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fspm,ch-bit-swizzling = /bits/ 8 <
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/* LP4_PHYS_CH0A */
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/* DQA[0:7] pins of LPDDR4 module */
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6 7 5 4 3 1 0 2
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/* DQA[8:15] pins of LPDDR4 module */
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12 10 11 13 14 8 9 15
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/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
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16 22 23 20 18 17 19 21
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/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
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30 28 29 25 24 26 27 31
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/* LP4_PHYS_CH0B */
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/* DQA[0:7] pins of LPDDR4 module */
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7 3 5 2 6 0 1 4
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/* DQA[8:15] pins of LPDDR4 module */
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9 14 12 13 10 11 8 15
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/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
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20 22 23 16 19 17 18 21
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/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
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28 24 26 27 29 30 31 25
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/* LP4_PHYS_CH1A */
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/* DQA[0:7] pins of LPDDR4 module */
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2 1 6 7 5 4 3 0
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/* DQA[8:15] pins of LPDDR4 module */
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11 10 8 9 12 15 13 14
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/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
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17 23 19 16 21 22 20 18
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/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
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31 29 26 25 28 27 24 30
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/* LP4_PHYS_CH1B */
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/* DQA[0:7] pins of LPDDR4 module */
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4 3 7 5 6 1 0 2
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/* DQA[8:15] pins of LPDDR4 module */
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15 9 8 11 14 13 12 10
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/* DQB[0:7] pins of LPDDR4 module with offset of 16 */
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20 23 22 21 18 19 16 17
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/* DQB[7:15] pins of LPDDR4 module with offset of 16 */
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25 28 30 31 26 27 24 29>;
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};
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