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https://github.com/brain-hackers/u-boot-brain
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cd40b82655
Add additional fields. They will be just recorded and filled but not shown. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
88 lines
1.8 KiB
C
88 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2019 Xilinx, Inc.
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* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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*/
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#ifndef __FRU_H
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#define __FRU_H
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struct fru_common_hdr {
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u8 version;
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u8 off_internal;
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u8 off_chassis;
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u8 off_board;
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u8 off_product;
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u8 off_multirec;
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u8 pad;
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u8 crc;
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};
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#define FRU_BOARD_MAX_LEN 32
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struct __packed fru_board_info_header {
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u8 ver;
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u8 len;
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u8 lang_code;
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u8 time[3];
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};
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struct __packed fru_board_info_member {
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u8 type_len;
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u8 *name;
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};
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struct fru_board_data {
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u8 ver;
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u8 len;
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u8 lang_code;
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u8 time[3];
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u8 manufacturer_type_len;
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u8 manufacturer_name[FRU_BOARD_MAX_LEN];
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u8 product_name_type_len;
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u8 product_name[FRU_BOARD_MAX_LEN];
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u8 serial_number_type_len;
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u8 serial_number[FRU_BOARD_MAX_LEN];
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u8 part_number_type_len;
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u8 part_number[FRU_BOARD_MAX_LEN];
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u8 file_id_type_len;
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u8 file_id[FRU_BOARD_MAX_LEN];
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/* Xilinx custom fields */
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u8 rev_type_len;
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u8 rev[FRU_BOARD_MAX_LEN];
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u8 pcie_type_len;
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u8 pcie[FRU_BOARD_MAX_LEN];
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u8 uuid_type_len;
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u8 uuid[FRU_BOARD_MAX_LEN];
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};
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struct fru_table {
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struct fru_common_hdr hdr;
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struct fru_board_data brd;
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bool captured;
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};
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#define FRU_TYPELEN_CODE_MASK 0xC0
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#define FRU_TYPELEN_LEN_MASK 0x3F
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#define FRU_COMMON_HDR_VER_MASK 0xF
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#define FRU_COMMON_HDR_LEN_MULTIPLIER 8
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#define FRU_LANG_CODE_ENGLISH 0
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#define FRU_LANG_CODE_ENGLISH_1 25
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#define FRU_TYPELEN_EOF 0xC1
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/* This should be minimum of fields */
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#define FRU_BOARD_AREA_TOTAL_FIELDS 5
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#define FRU_TYPELEN_TYPE_SHIFT 6
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#define FRU_TYPELEN_TYPE_BINARY 0
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#define FRU_TYPELEN_TYPE_ASCII8 3
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int fru_display(int verbose);
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int fru_capture(unsigned long addr);
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int fru_generate(unsigned long addr, char *manufacturer, char *board_name,
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char *serial_no, char *part_no, char *revision);
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u8 fru_checksum(u8 *addr, u8 len);
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extern struct fru_table fru_data;
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#endif /* FRU_H */
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