mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
177 lines
3.4 KiB
C
177 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 Toradex
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*/
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#include <common.h>
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#include <command.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mm_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/mach-imx/boot_mode.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <cpu_func.h>
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#include <dm/device.h>
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#include <dm/device-internal.h>
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#include <dm/uclass.h>
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#include <dm/uclass-internal.h>
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#include <hang.h>
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#include <i2c.h>
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#include <power/bd71837.h>
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#include <power/pca9450.h>
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#include <power/pmic.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define I2C_PMIC_BUS_ID 1
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int spl_board_boot_device(enum boot_device boot_dev_spl)
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{
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switch (boot_dev_spl) {
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case MMC1_BOOT:
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return BOOT_DEVICE_MMC1;
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case SD2_BOOT:
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case MMC2_BOOT:
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return BOOT_DEVICE_MMC2;
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case SD3_BOOT:
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case MMC3_BOOT:
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return BOOT_DEVICE_MMC1;
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case USB_BOOT:
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return BOOT_DEVICE_BOARD;
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default:
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return BOOT_DEVICE_NONE;
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}
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}
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void spl_dram_init(void)
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{
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ddr_init(&dram_timing);
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}
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void spl_board_init(void)
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{
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/* Serial download mode */
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if (is_usb_boot()) {
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puts("Back to ROM, SDP\n");
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restore_boot_params();
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}
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puts("Normal Boot\n");
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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#define UART_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE4)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
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/* Verdin UART_3, Console/Debug UART */
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static iomux_v3_cfg_t const uart_pads[] = {
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IMX8MM_PAD_SAI2_RXFS_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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IMX8MM_PAD_SAI2_RXC_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static iomux_v3_cfg_t const wdog_pads[] = {
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IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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int board_early_init_f(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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return 0;
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}
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int power_init_board(void)
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{
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struct udevice *dev;
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int ret;
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if (IS_ENABLED(CONFIG_SPL_DM_PMIC_PCA9450)) {
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ret = pmic_get("pmic", &dev);
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if (ret == -ENODEV) {
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puts("No pmic found\n");
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return ret;
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}
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if (ret != 0)
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return ret;
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/* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
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pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
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/* increase VDD_DRAM to 0.975v for 1.5Ghz DDR */
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pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
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/* set WDOG_B_CFG to cold reset */
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pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
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pmic_reg_write(dev, PCA9450_CONFIG2, 0x1);
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return 0;
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}
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return 0;
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}
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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arch_cpu_init();
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init_uart_clk(0);
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board_early_init_f();
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timer_init();
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preloader_console_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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ret = uclass_get_device_by_name(UCLASS_CLK,
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"clock-controller@30380000",
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&dev);
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if (ret < 0) {
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printf("Failed to find clock node. Check device tree\n");
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hang();
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}
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enable_tzc380();
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power_init_board();
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/* DDR initialization */
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spl_dram_init();
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board_init_r(NULL, 0);
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}
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