mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
35b65dd8ef
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
367 lines
8.9 KiB
C
367 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016-2018 Toradex AG
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <net.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx7-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/io.h>
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#include <common.h>
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#include <dm.h>
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#include <dm/platform_data/serial_mxc.h>
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#include <fdt_support.h>
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#include <fsl_esdhc_imx.h>
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#include <jffs2/load_kernel.h>
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#include <linux/delay.h>
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#include <linux/sizes.h>
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#include <mmc.h>
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#include <miiphy.h>
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#include <mtd_node.h>
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#include <netdev.h>
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#include <power/pmic.h>
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#include <power/rn5t567_pmic.h>
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#include <usb.h>
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#include <usb/ehci-ci.h>
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#include "../common/tdx-common.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
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PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
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#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
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#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
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PAD_CTL_DSE_3P3V_49OHM)
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#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
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#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
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#define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size());
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return 0;
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}
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static iomux_v3_cfg_t const uart1_pads[] = {
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MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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#ifdef CONFIG_USB_EHCI_MX7
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static iomux_v3_cfg_t const usb_cdet_pads[] = {
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MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#endif
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#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
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static iomux_v3_cfg_t const gpmi_pads[] = {
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MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
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MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
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};
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static void setup_gpmi_nand(void)
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{
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imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
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/* NAND_USDHC_BUS_CLK is set in rom */
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set_clk_nand();
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}
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#endif
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#ifdef CONFIG_DM_VIDEO
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static iomux_v3_cfg_t const backlight_pads[] = {
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/* Backlight On */
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MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* Backlight PWM<A> (multiplexed pin) */
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MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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#define GPIO_BL_ON IMX_GPIO_NR(5, 1)
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#define GPIO_PWM_A IMX_GPIO_NR(1, 8)
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static int setup_lcd(void)
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{
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imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
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/* Set BL_ON */
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gpio_request(GPIO_BL_ON, "BL_ON");
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gpio_direction_output(GPIO_BL_ON, 1);
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/* Set PWM<A> to full brightness (assuming inversed polarity) */
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gpio_request(GPIO_PWM_A, "PWM<A>");
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gpio_direction_output(GPIO_PWM_A, 0);
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return 0;
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}
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#endif
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/*
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* Backlight off before OS handover
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*/
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void board_preboot_os(void)
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{
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#ifdef CONFIG_DM_VIDEO
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gpio_direction_output(GPIO_PWM_A, 1);
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gpio_direction_output(GPIO_BL_ON, 0);
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#endif
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}
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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#ifdef CONFIG_FEC_MXC
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
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= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
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/*
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* Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
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* and output it on the pin
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*/
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clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
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IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
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IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
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#else
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/* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
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clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
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IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
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IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
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#endif
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return set_clk_enet(ENET_50MHZ);
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#ifdef CONFIG_FEC_MXC
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setup_fec();
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#endif
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#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND
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setup_gpmi_nand();
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#endif
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#ifdef CONFIG_USB_EHCI_MX7
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imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
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gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
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#endif
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return 0;
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}
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#ifdef CONFIG_DM_PMIC
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int power_init_board(void)
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{
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struct udevice *dev;
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int reg, ver;
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int ret;
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ret = pmic_get("rn5t567@33", &dev);
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if (ret)
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return ret;
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ver = pmic_reg_read(dev, RN5T567_LSIVER);
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reg = pmic_reg_read(dev, RN5T567_OTPVER);
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printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
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/* set judge and press timer of N_OE to minimal values */
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pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
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/* configure sleep slot for 3.3V Ethernet */
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reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
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reg = (reg & 0xf0) | reg >> 4;
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pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
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/* disable DCDC2 discharge to avoid backfeeding through VFB2 */
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pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
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/* configure sleep slot for ARM rail */
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reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
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reg = (reg & 0xf0) | reg >> 4;
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pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
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/* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
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pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
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return 0;
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}
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void reset_cpu(void)
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{
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struct udevice *dev;
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pmic_get("rn5t567@33", &dev);
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/* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
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pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
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pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
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/*
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* Re-power factor detection on PMIC side is not instant. 1ms
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* proved to be enough time until reset takes effect.
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*/
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mdelay(1);
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}
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#endif
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int checkboard(void)
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{
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printf("Model: Toradex Colibri iMX7%c\n",
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is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
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return 0;
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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#if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY)
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int up;
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up = arch_auxiliary_core_check_up(0);
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if (up) {
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int ret;
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int areas = 1;
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u64 start[2], size[2];
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/*
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* Reserve 1MB of memory for M4 (1MiB is also the minimum
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* alignment for Linux due to MMU section size restrictions).
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*/
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start[0] = gd->bd->bi_dram[0].start;
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size[0] = SZ_256M - SZ_1M;
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/* If needed, create a second entry for memory beyond 256M */
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if (gd->bd->bi_dram[0].size > SZ_256M) {
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start[1] = gd->bd->bi_dram[0].start + SZ_256M;
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size[1] = gd->bd->bi_dram[0].size - SZ_256M;
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areas = 2;
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}
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ret = fdt_set_usable_memory(blob, start, size, areas);
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if (ret) {
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eprintf("Cannot set usable memory\n");
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return ret;
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}
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} else {
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int off;
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off = fdt_node_offset_by_compatible(blob, -1,
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"fsl,imx7d-rpmsg");
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if (off > 0)
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fdt_status_disabled(blob, off);
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}
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#endif
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#if defined(CONFIG_FDT_FIXUP_PARTITIONS)
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static const struct node_info nodes[] = {
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{ "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
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{ "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, },
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};
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/* Update partition nodes using info from mtdparts env var */
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puts(" Updating MTD partitions...\n");
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fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
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#endif
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return ft_common_board_setup(blob, bd);
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}
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#endif
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#ifdef CONFIG_USB_EHCI_MX7
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static iomux_v3_cfg_t const usb_otg2_pads[] = {
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MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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int board_ehci_hcd_init(int port)
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{
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switch (port) {
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case 0:
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break;
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case 1:
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if (is_cpu_type(MXC_CPU_MX7S))
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return -ENODEV;
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imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
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ARRAY_SIZE(usb_otg2_pads));
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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int board_usb_phy_mode(int port)
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{
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switch (port) {
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case 0:
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if (gpio_get_value(USB_CDET_GPIO))
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return USB_INIT_DEVICE;
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else
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return USB_INIT_HOST;
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case 1:
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default:
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return USB_INIT_HOST;
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}
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}
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int board_late_init(void)
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{
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#if defined(CONFIG_DM_VIDEO)
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setup_lcd();
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#endif
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return 0;
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}
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#endif
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