mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
85 lines
3.1 KiB
C
85 lines
3.1 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Altera SoCFPGA Clock and PLL configuration
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*/
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#ifndef __SOCFPGA_PLL_CONFIG_H__
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#define __SOCFPGA_PLL_CONFIG_H__
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#define CONFIG_HPS_DBCTRL_STAYOSC1 1
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#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
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#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
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#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
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#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
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#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
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#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
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#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
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#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
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#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
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#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
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#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
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#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
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#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
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#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
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#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
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#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
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#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
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#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
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#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
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#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
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#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
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#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
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#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
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#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
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#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
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#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
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#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
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#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
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#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
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#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
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#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
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#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
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#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
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#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
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#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
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#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
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#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
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#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
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#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
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#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
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#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
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#define CONFIG_HPS_CLK_OSC1_HZ 25000000
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#define CONFIG_HPS_CLK_OSC2_HZ 25000000
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#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
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#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
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#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
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#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
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#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
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#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
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#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
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#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
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#define CONFIG_HPS_CLK_NAND_HZ 50000000
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#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
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#define CONFIG_HPS_CLK_QSPI_HZ 400000000
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#define CONFIG_HPS_CLK_SPIM_HZ 12500000
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#define CONFIG_HPS_CLK_CAN0_HZ 12500000
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#define CONFIG_HPS_CLK_CAN1_HZ 12500000
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#define CONFIG_HPS_CLK_GPIODB_HZ 32000
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#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
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#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
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#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
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#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
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#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
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#endif /* __SOCFPGA_PLL_CONFIG_H__ */
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